55 lines
1.1 KiB
Systemverilog
55 lines
1.1 KiB
Systemverilog
module gb (
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input logic clk_i,
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input logic nreset_i
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);
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logic we;
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logic [15:0] address;
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logic [ 7:0] rdata;
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logic [ 7:0] wdata;
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logic rom_cs;
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logic [ 7:0] rom_rdata;
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logic hi_ram_cs;
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logic [ 7:0] hi_ram_rdata;
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cpu cpu_inst (
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.clk_i (clk_i),
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.nreset_i (nreset_i),
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.address_o(address),
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.rdata_i (rdata),
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.we_o (we),
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.wdata_o (wdata)
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);
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rom #(
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.FILE_NAME("DMG_ROM.bin"),
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.ADDR_W (8),
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.DATA_W (8)
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) rom_inst (
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.clk_i (clk_i),
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.cs_i (rom_cs),
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.address_i(address[7:0]),
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.rdata_o (rom_rdata)
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);
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ram #(
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.ADDR_W (7),
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.DATA_W (8)
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) hi_ram_inst (
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.clk_i (clk_i),
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.cs_i (hi_ram_cs),
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.address_i (address[6:0]),
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.rdata_o (hi_ram_rdata),
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.we_i (we),
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.wdata_i (wdata)
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);
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assign rom_cs = ~(|address[15:8]);
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assign hi_ram_cs = (&address[15:7]) & ~(&address[6:0]);
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assign rdata = rom_rdata | hi_ram_rdata;
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endmodule : gb
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