35 lines
668 B
Systemverilog
35 lines
668 B
Systemverilog
module ram #(
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parameter DATA_W = 8,
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parameter ADDR_W = 8
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)(
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input logic clk_i,
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input logic cs_i,
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input logic [ADDR_W-1:0] address_i,
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input logic we_i,
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input logic [DATA_W-1:0] wdata_i,
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output logic [DATA_W-1:0] rdata_o
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);
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localparam RAM_SIZE = 2**ADDR_W;
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logic [DATA_W-1:0] ram [RAM_SIZE-1:0];
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logic wenable;
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logic [DATA_W-1:0] rdata;
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assign wenable = cs_i & we_i;
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always_ff @(posedge clk_i)
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if (wenable)
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ram[address_i] <= wdata_i;
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always_ff @(posedge clk_i)
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if (cs_i)
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rdata <= ram[address_i];
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assign rdata_o = {DATA_W{cs_i}} & rdata;
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endmodule
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