31 lines
542 B
Systemverilog
31 lines
542 B
Systemverilog
module ppu (
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input logic clk,
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input logic nreset,
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input logic [15:0] cpu_addr_i,
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output logic [ 7:0] cpu_rdata_o,
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input logic cpu_we_i,
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input logic [ 7:0] cpu_wdata_i,
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output logic cpu_addr_sel_o
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);
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logic ly_sel;
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logic ly_r;
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logic ly_we;
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assign ly_sel = (cpu_addr_i == 16'hFF44);
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assign ly_we = ly_sel & cpu_we_i;
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always_ff @(posedge clk or negedge nreset) begin
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if (!nreset)
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ly_r <= 8'h90; // vsync hack
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else if (ly_we)
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ly_r <= 8'h90;
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end
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assign cpu_addr_sel_o = ly_sel;
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endmodule : ppu
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