93 lines
1.5 KiB
Tcl
93 lines
1.5 KiB
Tcl
if {$argc < 1} {
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puts "Usage: <command> $argv0 \[options\] \[sources\]"
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exit 1
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}
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set command [lindex $argv 0]
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set top ""
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set part ""
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set sources ""
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set output ""
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set i 1
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while {$i < $argc} {
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switch [lindex $argv $i] {
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-top {
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incr i
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if {$i >= $argc} {
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puts "Missing parameter after -top"
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exit 2
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}
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set top [lindex $argv $i]
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}
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-part {
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incr i
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if {$i >= $argc} {
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puts "Missing parameter after -part"
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exit 2
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}
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set part [lindex $argv $i]
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}
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-o {
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incr i
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if {$i >= $argc} {
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puts "Missing parameter after -o"
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exit 2
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}
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set output [lindex $argv $i]
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}
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default {
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lappend sources [lindex $argv $i]
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}
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}
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incr i
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}
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foreach src $sources {
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if {[string match "*.sv" $src] || [string match "*.v" $src]} {
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read_verilog "$src"
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}
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if {[string match "*.vhdl" $src]} {
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read_vhdl "$src"
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}
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if {[string match "*.xdc" $src]} {
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read_xdc "$src"
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}
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}
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if {[string length $top] <= 0} {
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puts "Error: top undefined (define with -top <name>)"
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exit 3
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}
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switch "$command" {
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sim {
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create_project -in_memory sim
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#launch_simulation
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}
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synth {
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if {[string length $part] <= 0} {
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puts "Error: part undefined (define with -part <name>)"
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exit 4
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}
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if {[string length $output] <= 0} {
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puts "Error: output undefined (define with -o <name>)"
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exit 4
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}
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synth_design -top "$top" -part "$part"
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opt_design
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place_design
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route_design
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write_bitstream -force "$output"
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}
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default {
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puts "Unknown command $command"
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exit 4
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}
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}
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