65 lines
1.6 KiB
Python
65 lines
1.6 KiB
Python
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from ReBba.Components.ExiRequest import ExiRequest
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from SimHelpers.ExiSimHelper import exiClockCycle, resetDut
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from amaranth import Const
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from amaranth.sim import Simulator
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import os
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class TestBench:
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def __init__(self):
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pass
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def requestTest(self):
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dut = self.dut
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yield dut.nen.eq(Const(0))
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def afterLow0():
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assert((yield dut.requestComplete) == 0)
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def afterLow1():
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assert((yield dut.requestComplete) == 1)
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for i in range(15):
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yield dut.exiIn.eq(~dut.exiIn)
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yield from exiClockCycle(dut.exiClkState, AfterLow=afterLow0)
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yield dut.exiIn.eq(~dut.exiIn)
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yield from exiClockCycle(dut.exiClkState, AfterLow=afterLow1)
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assert((yield dut.requestComplete) == 1)
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yield from exiClockCycle(dut.exiClkState)
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assert((yield dut.requestComplete) == 1)
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yield from resetDut(dut.rst)
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for i in range(15):
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yield dut.exiIn.eq(~dut.exiIn)
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yield from exiClockCycle(dut.exiClkState, AfterLow=afterLow0)
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yield dut.exiIn.eq(~dut.exiIn)
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yield from exiClockCycle(dut.exiClkState, AfterLow=afterLow1)
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def simulate(self):
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self.dut = ExiRequest()
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sim = Simulator(self.dut)
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sim.add_clock(1e-6) # 1 MHz
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sim.add_sync_process(self.requestTest)
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with sim.write_vcd(os.path.dirname(os.path.abspath(__file__)) + "/ExiRequest.vcd"):
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sim.run()
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#####
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# Main portion
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#####
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def main():
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bench = TestBench()
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bench.simulate()
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if __name__ == "__main__":
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main()
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