45 lines
862 B
Python
45 lines
862 B
Python
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import sys
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import os
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from amaranth import *
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from amaranth.back import verilog
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from amaranth.sim import Simulator
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from amaranth_boards.icebreaker import *;
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class ReBba:
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def __init__():
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pass
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class TestBench:
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def __init__(self):
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pass
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def simulate(self):
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pass
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def main():
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if(len(sys.argv) == 2):
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if sys.argv[1] == "s":
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bench = TestBench()
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bench.simulate()
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if sys.argv[1] == "v":
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mod = ReBba()
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with open(os.path.dirname(os.path.abspath(__file__)) + "/bba.v", "w") as f:
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f.write(verilog.convert(mod, ports=[mod.exiClk, mod.inb, mod.data]))
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if sys.argv[1] == "p":
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mod = ReBba()
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else:
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bench = TestBench()
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bench.simulate()
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#####
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# Main portion
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#####
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if __name__ == "__main__":
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main()
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