Restructured the amaranth HDL files.

re-bba/ShiftRegister/ShiftRegister.py

@@ -2,7 +2,6 @@
 import sys
 import os
 from amaranth import *
-from amaranth_boards.icebreaker import *
 from amaranth.back import verilog
 from amaranth.sim import Simulator
 
@@ -139,9 +138,6 @@ def main():
             mod = ShiftRegister(8)
             with open(os.path.dirname(os.path.abspath(__file__)) + "/shift_register.v", "w") as f:
                 f.write(verilog.convert(mod, ports=[mod.exiClk, mod.inb, mod.data]))
-
-        if sys.argv[1] == "p":
-            ICEBreakerPlatform().build(ShiftRegister(8), do_program=True)
     
     else:
         bench = TestBench()

re-bba/re-bba.py

@@ -0,0 +1,44 @@
+import sys
+import os
+from amaranth import *
+from amaranth.back import verilog
+from amaranth.sim import Simulator
+from amaranth_boards.icebreaker import *;
+
+class ReBba:
+    def __init__():
+        pass
+
+class TestBench:
+    def __init__(self):
+        pass
+
+    def simulate(self):
+        pass
+
+def main():
+    if(len(sys.argv) == 2):
+
+        if sys.argv[1] == "s":
+            bench = TestBench()
+            bench.simulate()
+        
+        if sys.argv[1] == "v":
+            mod = ReBba()
+            with open(os.path.dirname(os.path.abspath(__file__)) + "/bba.v", "w") as f:
+                f.write(verilog.convert(mod, ports=[mod.exiClk, mod.inb, mod.data]))
+
+        if sys.argv[1] == "p":
+            mod = ReBba()
+    
+    else:
+        bench = TestBench()
+        bench.simulate()
+
+
+#####
+# Main portion
+#####
+
+if __name__ == "__main__":
+    main()