Fixes clock cycle delay in propagation of ExiClockState

This commit is contained in:
Dennis Brentjes 2022-01-11 22:47:25 +01:00
parent 43fb4beb6e
commit 386602a63c
2 changed files with 5 additions and 9 deletions

View File

@ -31,14 +31,14 @@ class ExiClock(Elaboratable):
with m.If(self.prevExiClkValid):
with m.If(self.prevExiClkState == ClockState.FALLING):
m.d.sync += self.exiClkState.eq(ClockState.LOW)
m.d.comb += self.exiClkState.eq(ClockState.LOW)
with m.Elif(self.prevExiClkState == ClockState.RISING):
m.d.sync += self.exiClkState.eq(ClockState.HIGH)
m.d.comb += self.exiClkState.eq(ClockState.HIGH)
with m.Else():
with m.If(self.prevExiClk ^ self.exiClk):
m.d.sync += self.exiClkState.eq(Cat(1, self.exiClk))
m.d.comb += self.exiClkState.eq(Cat(1, self.exiClk))
with m.Else():
m.d.sync += self.exiClkState.eq(Cat(0, self.exiClk))
m.d.comb += self.exiClkState.eq(Cat(0, self.exiClk))
m.d.sync += self.prevExiClkState.eq(self.exiClkState)
@ -64,19 +64,14 @@ class TestBench:
yield
yield from self.FlipExiClock(dut)
yield
yield
assert (yield dut.exiClkState) == ClockState.RISING.value
yield
yield
assert (yield dut.exiClkState) == ClockState.HIGH.value
yield
yield
yield from self.FlipExiClock(dut)
yield
yield
assert (yield dut.exiClkState) == ClockState.FALLING.value
yield
yield
assert (yield dut.exiClkState) == ClockState.LOW.value
yield

View File

@ -1,5 +1,6 @@
import os
import sys
from amaranth import *
from amaranth.build import Platform
from amaranth.back import verilog