110 lines
2.8 KiB
Python
110 lines
2.8 KiB
Python
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import enum
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import sys
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import os
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from amaranth.build import Platform
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from amaranth import *
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from amaranth.sim import Simulator
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class ClockState(enum.Enum):
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LOW = 0
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FALLING = 1
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HIGH = 2
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RISING = 3
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class ExiClock(Elaboratable):
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def __init__(self):
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# Ports
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self.exiClk = Signal()
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self.exiClkState = Signal(2)
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# State
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self.prevExiClkValid = Signal()
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self.prevExiClk = Signal()
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self.prevExiClkState = Signal(2)
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def elaborate(self, platform: Platform):
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m = Module()
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with m.If(self.prevExiClkValid):
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with m.If(self.prevExiClkState == ClockState.FALLING):
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m.d.comb += self.exiClkState.eq(ClockState.LOW)
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with m.Elif(self.prevExiClkState == ClockState.RISING):
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m.d.comb += self.exiClkState.eq(ClockState.HIGH)
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with m.Else():
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with m.If(self.prevExiClk ^ self.exiClk):
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m.d.comb += self.exiClkState.eq(Cat(1, self.exiClk))
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with m.Else():
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m.d.comb += self.exiClkState.eq(Cat(0, self.exiClk))
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m.d.sync += self.prevExiClkState.eq(self.exiClkState)
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m.d.sync += self.prevExiClk.eq(self.exiClk)
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m.d.sync += self.prevExiClkValid.eq(1)
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return m
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#####
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# TestBench
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#####
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class TestBench:
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def __init__(self):
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pass
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def FlipExiClock(self, dut):
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yield dut.exiClk.eq(~dut.exiClk)
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def clockTest(self):
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dut = self.dut
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yield dut.exiClk.eq(0)
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yield
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yield from self.FlipExiClock(dut)
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yield
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assert (yield dut.exiClkState) == ClockState.RISING.value
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yield
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assert (yield dut.exiClkState) == ClockState.HIGH.value
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yield
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yield from self.FlipExiClock(dut)
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yield
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assert (yield dut.exiClkState) == ClockState.FALLING.value
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yield
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assert (yield dut.exiClkState) == ClockState.LOW.value
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yield
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def simulate(self):
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self.dut = ExiClock()
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sim = Simulator(self.dut)
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sim.add_clock(1e-6) # 1 MHz
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sim.add_sync_process(self.clockTest)
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with sim.write_vcd(os.path.dirname(os.path.abspath(__file__)) + "/ExiClock.vcd"):
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sim.run()
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#####
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# Main portion
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#####
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def main():
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if(len(sys.argv) == 2):
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if sys.argv[1] == "s":
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bench = TestBench()
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bench.simulate()
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if sys.argv[1] == "v":
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mod = ExiClock()
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with open(os.path.dirname(os.path.abspath(__file__)) + "/ExiClock.v", "w") as f:
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f.write(verilog.convert(mod, ports=[mod.exiClk, mod.exiClkState]))
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else:
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bench = TestBench()
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bench.simulate()
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if __name__ == "__main__":
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main() |