Fixes clock cycle delay in propagation of ExiClockState

re-bba/ExiClock.py

@@ -31,14 +31,14 @@ class ExiClock(Elaboratable):
 
         with m.If(self.prevExiClkValid):
             with m.If(self.prevExiClkState == ClockState.FALLING):
-                m.d.sync += self.exiClkState.eq(ClockState.LOW)
+                m.d.comb += self.exiClkState.eq(ClockState.LOW)
             with m.Elif(self.prevExiClkState == ClockState.RISING):
-                m.d.sync += self.exiClkState.eq(ClockState.HIGH)
+                m.d.comb += self.exiClkState.eq(ClockState.HIGH)
             with m.Else():
                 with m.If(self.prevExiClk ^ self.exiClk):
-                    m.d.sync += self.exiClkState.eq(Cat(1, self.exiClk))
+                    m.d.comb += self.exiClkState.eq(Cat(1, self.exiClk))
                 with m.Else():
-                    m.d.sync += self.exiClkState.eq(Cat(0, self.exiClk))
+                    m.d.comb += self.exiClkState.eq(Cat(0, self.exiClk))
 
             m.d.sync += self.prevExiClkState.eq(self.exiClkState)
             
@@ -64,19 +64,14 @@ class TestBench:
         yield
         yield from self.FlipExiClock(dut)
         yield
-        yield
         assert (yield dut.exiClkState) == ClockState.RISING.value
         yield
-        yield
         assert (yield dut.exiClkState) == ClockState.HIGH.value
         yield
-        yield
         yield from self.FlipExiClock(dut)
         yield
-        yield
         assert (yield dut.exiClkState) == ClockState.FALLING.value
         yield
-        yield
         assert (yield dut.exiClkState) == ClockState.LOW.value
         yield
 

re-bba/ShiftRegister.py

@@ -1,5 +1,6 @@
 
 import os
+import sys
 from amaranth import *
 from amaranth.build import Platform
 from amaranth.back import verilog