Restructured Amaranth code to be able to import sibling modules

re-bba/ReBba/Components/Debouncer.py

@@ -0,0 +1,39 @@
+
+from amaranth.build import Platform
+from amaranth import *
+
+class Debouncer(Elaboratable):
+
+    def __init__(self, cycles: int):
+        #signals
+        self.input = Signal()
+        self.output = Signal()
+
+        #state
+        self.count = Signal(range(0, cycles+1), reset=cycles)
+        self.state = Signal()
+        self.prevInValid = Signal()
+        self.prevIn = Signal()
+
+    def elaborate(self, platform: Platform):
+        m = Module()
+
+        with m.If(self.prevInValid):
+            with m.If(self.count == 0):
+                with m.If(self.prevIn ^ self.input):
+                    m.d.sync += self.count.eq(self.count.reset)
+                m.d.sync += self.state.eq(self.input)
+            with m.Elif(self.input == self.state):
+                m.d.sync += self.count.eq(self.count.reset)
+                m.d.sync += self.state.eq(self.input)
+            with m.Else():
+                m.d.sync += self.count.eq(self.count - 1)        
+        with m.Else():
+            m.d.sync += self.count.eq(0)
+            m.d.sync += self.prevInValid.eq(Const(1))
+            m.d.sync += self.state.eq(self.input)
+
+        m.d.sync += self.prevIn.eq(self.input)
+        m.d.comb += self.output.eq(self.state)
+
+        return m

re-bba/ReBba/Components/ExiClock.py

@@ -0,0 +1,45 @@
+
+import enum
+
+from amaranth.build import Platform
+from amaranth import *
+
+class ClockState(enum.Enum):
+    LOW     = 0
+    FALLING = 1
+    HIGH    = 2
+    RISING  = 3
+
+class ExiClock(Elaboratable):
+
+    def __init__(self):
+        # Ports
+        self.exiClk = Signal()
+        self.exiClkState = Signal(2)
+
+        # State
+        self.prevExiClkValid = Signal()
+        self.prevExiClk = Signal()
+        self.prevExiClkState = Signal(2)
+
+    
+    def elaborate(self, platform: Platform):
+        m = Module()
+
+        with m.If(self.prevExiClkValid):
+            with m.If(self.prevExiClkState == ClockState.FALLING):
+                m.d.comb += self.exiClkState.eq(ClockState.LOW)
+            with m.Elif(self.prevExiClkState == ClockState.RISING):
+                m.d.comb += self.exiClkState.eq(ClockState.HIGH)
+            with m.Else():
+                with m.If(self.prevExiClk ^ self.exiClk):
+                    m.d.comb += self.exiClkState.eq(Cat(1, self.exiClk))
+                with m.Else():
+                    m.d.comb += self.exiClkState.eq(Cat(0, self.exiClk))
+
+            m.d.sync += self.prevExiClkState.eq(self.exiClkState)
+            
+        m.d.sync += self.prevExiClk.eq(self.exiClk)
+        m.d.sync += self.prevExiClkValid.eq(1)
+        
+        return m

re-bba/ReBba/Components/ExiDecoder.py

@@ -0,0 +1,23 @@
+from amaranth.build import Platform
+from amaranth import *
+
+from ExiDecoders.GetId import GetId
+
+class ExiDecoder(Elaboratable):
+    
+    def __init__(self):
+        #ports
+        self.request = Signal(16)
+        self.request_type = Signal(1)
+        #state
+
+    def elaborate(self, platform: Platform):
+        m = Module()
+
+        getId = GetId()
+        m.submodules += getId
+
+        m.d.comb += getId.request.eq(self.request)
+        m.d.comb += self.request_type[0].eq(getId.isGetId)
+
+        return m

re-bba/ReBba/Components/ExiRequest.py

@@ -0,0 +1,51 @@
+
+from ReBba.Components.ShiftRegister import ShiftRegister
+from ReBba.Components.ExiClock import ClockState
+
+from amaranth import Const, Elaboratable, Module, Signal
+from amaranth.build import Platform
+
+
+class ExiRequest(Elaboratable):
+    
+    def __init__(self):
+        #ports
+        self.request = Signal(16)
+        self.nen = Signal(1)
+        self.rst = Signal(1)
+        self.exiClkState = Signal(2)
+        self.exiIn = Signal(1)
+        self.requestComplete = Signal(1)
+
+        #state
+        self.disableShift = Signal(1, reset=0)
+        self.shiftRegister = ShiftRegister(16)
+        self.clockCount = Signal(5, reset=0)
+
+    def elaborate(self, platform: Platform):
+        m = Module()
+
+        m.submodules += self.shiftRegister
+
+        m.d.comb += self.request.eq(self.shiftRegister.data)
+        m.d.comb += self.shiftRegister.inb.eq(self.exiIn)
+        m.d.comb += self.shiftRegister.exiClkState.eq(self.exiClkState)
+        m.d.comb += self.shiftRegister.nen.eq(self.disableShift)
+
+        with m.If(~self.nen):
+            with m.If(self.clockCount != 16):
+                with m.If(self.exiClkState == ClockState.FALLING):
+                    m.d.sync += self.clockCount.eq(self.clockCount + 1)
+                
+            with m.If(self.clockCount == 16):
+                m.d.comb += self.disableShift.eq(Const(1))
+                m.d.comb += self.requestComplete.eq(Const(1))
+
+        with m.If(self.rst):
+            m.d.comb += self.request.eq(self.request.reset)
+            m.d.sync += self.clockCount.eq(self.clockCount.reset)
+            m.d.comb += self.disableShift.eq(self.disableShift.reset)
+
+        m.d.comb += self.shiftRegister.rst.eq(self.rst)
+
+        return m

re-bba/ReBba/Components/ShiftRegister.py

@@ -0,0 +1,29 @@
+
+from ReBba.Components.ExiClock import ClockState
+
+from amaranth import *
+from amaranth.build import Platform
+
+class ShiftRegister(Elaboratable):
+    def __init__(self, width):
+        self.width = width
+
+        # Ports
+        self.nen = Signal()
+        self.exiClkState = Signal(2)
+        self.rst = Signal()
+        self.inb = Signal()
+        self.data = Signal(self.width, reset=0)
+
+    def elaborate(self, platform: Platform):
+        m = Module()
+
+        with m.If(self.rst):
+            m.d.sync += self.data.eq(self.data.reset)
+
+        with m.If(~self.nen):
+            with m.If(self.exiClkState == ClockState.FALLING):
+                m.d.sync += self.data.eq(self.data.shift_left(1) | self.inb )
+
+        return m
+