51 lines
1.7 KiB
Python
51 lines
1.7 KiB
Python
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from ReBba.Components.ShiftRegister import ShiftRegister
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from ReBba.Components.ExiClock import ClockState
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from amaranth import Const, Elaboratable, Module, Signal
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from amaranth.build import Platform
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class ExiRequest(Elaboratable):
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def __init__(self):
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#ports
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self.request = Signal(16)
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self.nen = Signal(1)
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self.rst = Signal(1)
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self.exiClkState = Signal(2)
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self.exiIn = Signal(1)
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self.requestComplete = Signal(1)
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#state
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self.disableShift = Signal(1, reset=0)
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self.shiftRegister = ShiftRegister(16)
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self.clockCount = Signal(5, reset=0)
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def elaborate(self, platform: Platform):
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m = Module()
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m.submodules += self.shiftRegister
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m.d.comb += self.request.eq(self.shiftRegister.data)
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m.d.comb += self.shiftRegister.inb.eq(self.exiIn)
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m.d.comb += self.shiftRegister.exiClkState.eq(self.exiClkState)
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m.d.comb += self.shiftRegister.nen.eq(self.disableShift)
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with m.If(~self.nen):
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with m.If(self.clockCount != 16):
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with m.If(self.exiClkState == ClockState.FALLING):
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m.d.sync += self.clockCount.eq(self.clockCount + 1)
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with m.If(self.clockCount == 16):
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m.d.comb += self.disableShift.eq(Const(1))
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m.d.comb += self.requestComplete.eq(Const(1))
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with m.If(self.rst):
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m.d.comb += self.request.eq(self.request.reset)
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m.d.sync += self.clockCount.eq(self.clockCount.reset)
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m.d.comb += self.disableShift.eq(self.disableShift.reset)
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m.d.comb += self.shiftRegister.rst.eq(self.rst)
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return m |