Restructured Amaranth code to be able to import sibling modules

re-bba/ReBba/TestBenches/DebouncerTb.py

@@ -0,0 +1,54 @@
+from ReBba.Components.Debouncer import Debouncer
+
+from amaranth import Const
+from amaranth.sim import Simulator
+
+import os
+
+class TestBench:
+    def __init__(self):
+        pass
+
+    def holdTest(self):
+        dut = self.dut
+        yield
+        yield
+
+        yield dut.input.eq(Const(1))
+        yield
+        yield dut.input.eq(Const(0))
+        yield
+
+        for _ in range(5):
+            assert(yield(dut.output) == 1)
+            yield
+
+        yield dut.input.eq(Const(1))
+        yield
+        yield dut.input.eq(Const(0))
+        yield
+
+        for _ in range(16):
+            assert(yield(dut.output) == 1)
+            yield
+
+        assert(yield(dut.output) == 0)
+        yield
+        yield
+
+    def simulate(self):
+        self.dut = Debouncer(15)
+
+        sim = Simulator(self.dut)
+        sim.add_clock(1e-6) # 1 MHz
+        sim.add_sync_process(self.holdTest)
+
+        with sim.write_vcd(os.path.dirname(os.path.abspath(__file__)) + "/Debouncer.vcd"):
+            sim.run()
+
+def main():
+    bench = TestBench()
+    bench.simulate()
+
+if __name__ == "__main__":
+    main()

re-bba/ReBba/TestBenches/ExiClockTb.py

@@ -0,0 +1,48 @@
+from ReBba.Components.ExiClock import ClockState, ExiClock
+from ReBba.TestBenches.SimHelpers.ExiSimHelper import exiClockCycle
+
+from amaranth.sim  import Simulator
+
+import os
+
+class TestBench:
+    def __init__(self):
+        pass
+
+    def FlipExiClock(self, dut):
+        yield dut.exiClk.eq(~dut.exiClk)
+
+    def clockTest(self):
+        dut = self.dut
+
+        yield dut.exiClk.eq(0)
+        yield
+        yield from self.FlipExiClock(dut)
+        yield
+        assert (yield dut.exiClkState) == ClockState.RISING.value
+        yield
+        assert (yield dut.exiClkState) == ClockState.HIGH.value
+        yield
+        yield from self.FlipExiClock(dut)
+        yield
+        assert (yield dut.exiClkState) == ClockState.FALLING.value
+        yield
+        assert (yield dut.exiClkState) == ClockState.LOW.value
+        yield
+
+    def simulate(self):
+        self.dut = ExiClock()
+
+        sim = Simulator(self.dut)
+        sim.add_clock(1e-6) # 1 MHz
+        sim.add_sync_process(self.clockTest)
+
+        with sim.write_vcd(os.path.dirname(os.path.abspath(__file__)) + "/ExiClock.vcd"):
+            sim.run()
+
+def main():
+        bench = TestBench()
+        bench.simulate()
+
+if __name__ == "__main__":
+    main()

re-bba/ReBba/TestBenches/ExiRequestTb.py

@@ -0,0 +1,65 @@
+from ReBba.Components.ExiRequest import ExiRequest
+
+from SimHelpers.ExiSimHelper import exiClockCycle, resetDut
+
+from amaranth import Const
+from amaranth.sim import Simulator
+
+import os
+
+class TestBench:
+    def __init__(self):
+        pass
+
+    def requestTest(self):
+        dut = self.dut
+
+        yield dut.nen.eq(Const(0))
+
+        def afterLow0():
+            assert((yield dut.requestComplete) == 0)
+
+        def afterLow1():
+            assert((yield dut.requestComplete) == 1)
+
+
+        for i in range(15):
+            yield dut.exiIn.eq(~dut.exiIn)
+            yield from exiClockCycle(dut.exiClkState, AfterLow=afterLow0)
+
+        yield dut.exiIn.eq(~dut.exiIn)
+        yield from exiClockCycle(dut.exiClkState, AfterLow=afterLow1)
+
+        assert((yield dut.requestComplete) == 1)
+        yield from exiClockCycle(dut.exiClkState)
+        assert((yield dut.requestComplete) == 1)
+
+        yield from resetDut(dut.rst)
+
+        for i in range(15):
+            yield dut.exiIn.eq(~dut.exiIn)
+            yield from exiClockCycle(dut.exiClkState, AfterLow=afterLow0)
+
+        yield dut.exiIn.eq(~dut.exiIn)
+        yield from exiClockCycle(dut.exiClkState, AfterLow=afterLow1)
+
+    def simulate(self):
+        self.dut = ExiRequest()
+
+        sim = Simulator(self.dut)
+        sim.add_clock(1e-6) # 1 MHz
+        sim.add_sync_process(self.requestTest)
+
+        with sim.write_vcd(os.path.dirname(os.path.abspath(__file__)) + "/ExiRequest.vcd"):
+            sim.run()
+
+#####
+# Main portion
+#####
+
+def main():
+    bench = TestBench()
+    bench.simulate()
+
+if __name__ == "__main__":
+    main()

re-bba/ReBba/TestBenches/ShiftRegisterTb.py

@@ -0,0 +1,79 @@
+from amaranth import Elaboratable
+from ReBba.Components.ShiftRegister import ShiftRegister
+
+from ReBba.TestBenches.SimHelpers.ExiSimHelper import exiClockCycle
+
+from amaranth.sim import Simulator
+
+import os
+
+class TestBench:
+    def __init__(self):
+        pass
+
+    def enabled_test(self):
+        dut = self.dut
+
+        def afterAny():
+            assert not (yield dut.data)
+
+        # Disabled ShiftRegister should not Change.
+        yield dut.nen.eq(1)
+        for _ in range(10):
+            yield dut.inb.eq(~dut.inb)
+            yield from exiClockCycle(dut.exiClkState, AfterHigh=afterAny, AfterFalling=afterAny, AfterLow=afterAny, AfterRising=afterAny)
+
+    def normal_operation(self):
+        dut = self.dut
+
+        def oracle(i):
+            if i == 0: return 0x01
+            if i == 1: return 0x02
+            if i == 2: return 0x05
+            if i == 3: return 0x0A
+            if i == 4: return 0x15
+            if i == 5: return 0x2A
+            if i == 6: return 0x55
+            if i == 7: return 0xAA
+            if i == 8: return 0x55
+            if i == 9: return 0xAA
+
+        expectedOutput = 0
+
+        def afterLow():
+            assert (yield dut.data) == expectedOutput
+
+        yield dut.nen.eq(0)
+        for i in range(10):
+            expectedOutput = oracle(i)
+            yield dut.inb.eq(~dut.inb)
+            yield from exiClockCycle(dut.exiClkState, AfterLow=afterLow)
+
+    def simulate(self):
+        self.dut = ShiftRegister(8)
+
+        sim = Simulator(self.dut)
+        sim.add_clock(1e-6) # 1 MHz
+        sim.add_sync_process(self.enabled_test)
+
+        with sim.write_vcd(os.path.dirname(os.path.abspath(__file__)) + "/ShiftRegister_enable.vcd"):
+            sim.run()
+
+        self.dut = ShiftRegister(8)
+
+        sim = Simulator(self.dut)
+        sim.add_clock(1e-6) # 1 MHz
+        sim.add_sync_process(self.normal_operation)
+
+        with sim.write_vcd(os.path.dirname(os.path.abspath(__file__)) + "/ShiftRegister_shift.vcd"):
+            sim.run()
+
+def main():
+    bench = TestBench()
+    bench.simulate()
+
+if __name__ == "__main__":
+    main()
+
+
+

re-bba/ReBba/TestBenches/SimHelpers/ExiSimHelper.py

@@ -0,0 +1,30 @@
+from typing import Callable
+from ReBba.Components.ExiClock import ClockState
+from amaranth import Const, Elaboratable, Signal
+
+def empty():
+    yield None
+
+def exiClockCycle(exiClock: Signal, AfterHigh: Callable = empty, AfterFalling: Callable = empty, AfterLow: Callable = empty, AfterRising: Callable = empty):
+    yield exiClock.eq(ClockState.HIGH)
+    yield
+    yield from AfterHigh()
+    yield
+
+    yield exiClock.eq(ClockState.FALLING)
+    yield from AfterFalling()
+
+    yield exiClock.eq(ClockState.LOW)
+    yield
+    yield from AfterLow()
+    yield
+
+    yield exiClock.eq(ClockState.RISING)
+    yield from AfterRising()
+
+def resetDut(rst: Signal):
+    yield
+    yield rst.eq(Const(1))
+    yield
+    yield rst.eq(Const(0))
+    yield