48 lines
1.2 KiB
Python
48 lines
1.2 KiB
Python
from ReBba.Components.ExiClock import ClockState, ExiClock
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from ReBba.TestBenches.SimHelpers.ExiSimHelper import exiClockCycle
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from amaranth.sim import Simulator
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import os
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class TestBench:
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def __init__(self):
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pass
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def FlipExiClock(self, dut):
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yield dut.exiClk.eq(~dut.exiClk)
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def clockTest(self):
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dut = self.dut
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yield dut.exiClk.eq(0)
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yield
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yield from self.FlipExiClock(dut)
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yield
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assert (yield dut.exiClkState) == ClockState.RISING.value
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yield
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assert (yield dut.exiClkState) == ClockState.HIGH.value
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yield
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yield from self.FlipExiClock(dut)
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yield
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assert (yield dut.exiClkState) == ClockState.FALLING.value
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yield
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assert (yield dut.exiClkState) == ClockState.LOW.value
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yield
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def simulate(self):
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self.dut = ExiClock()
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sim = Simulator(self.dut)
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sim.add_clock(1e-6) # 1 MHz
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sim.add_sync_process(self.clockTest)
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with sim.write_vcd(os.path.dirname(os.path.abspath(__file__)) + "/ExiClock.vcd"):
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sim.run()
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def main():
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bench = TestBench()
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bench.simulate()
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if __name__ == "__main__":
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main() |