Restructured the amaranth HDL files.

This commit is contained in:
Dennis Brentjes 2022-01-09 15:12:27 +01:00
parent fd323b44e1
commit e0f186c304
4 changed files with 44 additions and 4 deletions

View File

@ -2,7 +2,6 @@
import sys
import os
from amaranth import *
from amaranth_boards.icebreaker import *
from amaranth.back import verilog
from amaranth.sim import Simulator
@ -140,9 +139,6 @@ def main():
with open(os.path.dirname(os.path.abspath(__file__)) + "/shift_register.v", "w") as f:
f.write(verilog.convert(mod, ports=[mod.exiClk, mod.inb, mod.data]))
if sys.argv[1] == "p":
ICEBreakerPlatform().build(ShiftRegister(8), do_program=True)
else:
bench = TestBench()
bench.simulate()

44
re-bba/re-bba.py Normal file
View File

@ -0,0 +1,44 @@
import sys
import os
from amaranth import *
from amaranth.back import verilog
from amaranth.sim import Simulator
from amaranth_boards.icebreaker import *;
class ReBba:
def __init__():
pass
class TestBench:
def __init__(self):
pass
def simulate(self):
pass
def main():
if(len(sys.argv) == 2):
if sys.argv[1] == "s":
bench = TestBench()
bench.simulate()
if sys.argv[1] == "v":
mod = ReBba()
with open(os.path.dirname(os.path.abspath(__file__)) + "/bba.v", "w") as f:
f.write(verilog.convert(mod, ports=[mod.exiClk, mod.inb, mod.data]))
if sys.argv[1] == "p":
mod = ReBba()
else:
bench = TestBench()
bench.simulate()
#####
# Main portion
#####
if __name__ == "__main__":
main()