Made new top level design which uses the shiftregister and connects leds and buttons

.gitignore

@@ -1 +1,2 @@
 .vscode
+build

re-bba/.gitignore

@@ -1 +1,3 @@
 *.vcd
+*.v
+**/__pycache__

re-bba/ShiftRegister/ShiftRegister.py

@@ -1,4 +1,5 @@
 
+import enum
 import sys
 import os
 from amaranth import *
@@ -9,23 +10,25 @@ from amaranth.sim import Simulator
 # Hardware Description.
 #####
 
+class ClockState(enum.Enum):
+    LOW     = 0
+    FALLING = 1
+    HIGH    = 2
+    RISING  = 3
+
 class ShiftRegister(Elaboratable):
     def __init__(self, width):
         self.width = width
 
         # Ports
         self.nen = Signal()
+        self.rst = Signal()
+
         self.inb = Signal()
         self.exiClk = Signal()
-
+        self.data = Signal(self.width, reset=0)
-        # Defines
-        self.LOW = 0
-        self.FALLING = 1
-        self.HIGH = 2
-        self.RISING = 3
 
         # State
-        self.data = Signal(self.width)
         self.prevExiClkValid = Signal()
         self.prevExiClk = Signal()
         self.prevExiClkState = Signal(2)
@@ -34,6 +37,9 @@ class ShiftRegister(Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
+        with m.If(self.rst):
+            m.d.sync += self.data.eq(self.data.reset)
+
         with m.If(~self.nen):
             with m.If(self.prevExiClkValid):
                 m.d.sync += self.prevExiClkState.eq(self.exiClkState)
@@ -42,7 +48,7 @@ class ShiftRegister(Elaboratable):
                 with m.Else():
                     m.d.sync += self.exiClkState.eq(Cat(self.exiClk, 0))
 
-                with m.If((self.exiClkState == self.FALLING).bool() & (self.exiClkState != self.prevExiClkState).bool()):
+                with m.If((self.exiClkState == ClockState.FALLING).bool() & (self.exiClkState != self.prevExiClkState).bool()):
                     m.d.sync += self.data.eq(self.data.shift_left(1) | self.inb )
 
             m.d.sync += self.prevExiClkValid.eq(1)

re-bba/re-bba.py

@@ -2,13 +2,46 @@ import sys
 import os
 from amaranth import *
 from amaranth.back import verilog
+from amaranth.build.plat import Platform
 from amaranth.sim import Simulator
 from amaranth_boards.icebreaker import *;
 
-class ReBba:
+from ShiftRegister.ShiftRegister import *;
-    def __init__():
+
+class ReBba(Elaboratable):
+    def __init__(self):
         pass
 
+    def elaborate(self, platform: Platform):
+        m = Module()
+
+        led1 = platform.request("led_g", 1)
+        led2 = platform.request("led_g", 4)
+        led3 = platform.request("led_g", 2)
+        led4 = platform.request("led_g", 3)
+        led5 = platform.request("led_r", 1)
+
+        btn1 = platform.request("button", 1)
+        btn2 = platform.request("button", 2)
+        btn3 = platform.request("button", 3)
+
+        sr = ShiftRegister(5)
+        m.submodules += sr
+
+        m.d.comb += led1.eq(sr.data[0])
+        m.d.comb += led2.eq(sr.data[1])
+        m.d.comb += led3.eq(sr.data[2])
+        m.d.comb += led4.eq(sr.data[3])
+        m.d.comb += led5.eq(sr.data[4])
+
+        m.d.comb += sr.exiClk.eq(btn3)
+        m.d.comb += sr.rst.eq(btn2)
+        m.d.comb += sr.inb.eq(btn1)
+
+        m.d.comb += sr.nen.eq(Const(0))
+
+        return m
+
 class TestBench:
     def __init__(self):
         pass
@@ -26,10 +59,13 @@ def main():
         if sys.argv[1] == "v":
             mod = ReBba()
             with open(os.path.dirname(os.path.abspath(__file__)) + "/bba.v", "w") as f:
-                f.write(verilog.convert(mod, ports=[mod.exiClk, mod.inb, mod.data]))
+                f.write(verilog.convert(mod, ports=[]))
 
         if sys.argv[1] == "p":
             mod = ReBba()
+            platform = ICEBreakerPlatform()
+            platform.add_resources(platform.break_off_pmod)
+            platform.build(mod, do_program=True)
     
     else:
         bench = TestBench()