eFuse V2.1 fix: datasheet-derived OVLO ladder + ILIM correction

Works the TPS25961 fix out from the datasheet rather than from memory, and
re-solves it against resistors already on the BOM.

OVLO: TI's 3-resistor ladder (eq 7/8) -> R46 620k->150k, R47 100k->10k, new
R48 12k + R49 2.2k (=14.2k).  UVLO 8.93 V typ, unchanged from today; OVLO
15.21 V typ, 15.81 V worst case.  The OVLO ceiling is set by U3 (TPS562201,
4.5-17 V input), not by the eFuse -- that rules out a tempting 3-resistor
solution tripping at 17.24 V.

ILIM: R45 100k -> 33k.  0.516 A sat BELOW the board's own 621 mA inrush, so
the part entered current limiting on every power-on (-> thermal shutdown ->
retries -> latch-off).  Inrush control comes from the fixed 5.17 V/ms slew
rate, not ILIM, so raising ILIM costs no inrush protection; it is pure fault
protection at ~27x the measured 56 mA load.

Every value is already stocked and 620k loses its only user: one FEWER unique
part, +2 placements.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>

hardware/re-bba-rb/TODO.md

@@ -245,10 +245,25 @@ schematic changes.
       2026-09-16, FAB-BLOCKER for V2.1).** OVLO (pin 2) is tied to GND, which on
       the TPS25961 selects the internal *fixed* overvoltage cutoff ~5.98 V — so a
       12 V rail is permanently in overvoltage lockout and the eFuse passes
-      nothing (bench-confirmed: 12V_EXI=0, GC_ON=0, W5100 unpowered). **Fix:**
-      OVLO divider off 12V_RAW, R_top ≈ 1.1 M / R_bottom ≈ 100 k → trip ~15 V.
-      See REVIEW.md eFuse entry. Bench workaround: feed 12 V onto 12V_EXI (C65+ /
-      U3 VIN) to bypass it. This must be fixed before any V2.1 fab order.
+      nothing (bench-confirmed: 12V_EXI=0, GC_ON=0, W5100 unpowered).
+      **FIX WORKED OUT FROM THE DATASHEET 2026-10-02 — values final, needs
+      schematic + PCB work.** TI 3-resistor ladder (§8.2.3.2), EN/UVLO tapped at
+      R1–R2 and OVLO at R2–R3, plus an ILIM correction:
+        R46  620 k -> **150 k**  (C93947)    R1, top: 12V_RAW -> EN/UVLO
+        R47  100 k -> **10 k**   (C25744)    R2: EN/UVLO -> OVLO
+        R48  NEW   -> **12 k**   (C25752)  \ R3 = 14.2 k in series,
+        R49  NEW   -> **2.2 k**  (C25879)  /      OVLO -> GND
+        R45  100 k -> **33 k**   (C25779)    ILIM 0.52 A -> 1.52 A
+        U13 pin 2 (OVLO): disconnect from GND, wire to the R47/R48 junction.
+      Gives UVLO 8.93 V typ (unchanged from today) and OVLO 15.21 V typ,
+      15.81 V worst case — under U3's 17 V input rating, which is what actually
+      caps the OVLO target. ILIM must exceed the board's own 621 mA inrush;
+      0.52 A did not, so the part current-limited on every power-on.
+      **Every value is already on the BOM and 620 k loses its only user, so this
+      is one FEWER unique part, +2 placements.** Full derivation, tolerance
+      analysis and the rejected alternatives are in REVIEW.md §eFuse.
+      Bench workaround meanwhile: feed 12 V onto 12V_EXI (C65+ / U3 VIN), or
+      lift U13 pin 2 (done on the lab unit). Must be fixed before any V2.1 fab.
 - [x] **D9 "USB" LED dark — OPEN SOLDER JOINT on its anode pad — FIXED by
       reflow 2026-09-30. Assembly defect on this unit, NOT a design bug.**
       Symptom: D9 never lights, on USB-only or GC power. Measured 3V3 on the