Fixes review comments.

hardware/re-bba-rb/REVIEW.md

@@ -69,12 +69,34 @@ datasheet extraction, WebSearch/WebFetch for parts and reference designs.
   earlier review note claiming they should be 1.8 V was wrong; do not "fix").
   VREGIN=3V3, VREGOUT→VCORE (1.8 V) with 4.7 µF + 3×100 nF on pins 12/37/64;
   4×VCCIO decoupled; REF = 12k 1 % to GND (DS requirement); RESET RC
-  (10k/100 nF); 12 MHz crystal Y1 (CL=12 pF part vs 18 pF caps — verified
-  consistent); TEST→GND, AGND→GND.
+  (10k/100 nF); 12 MHz crystal Y1 (CL=12 pF part vs 18 pF caps — re-verified
+  2026-07-31 against the real YXC datasheet + LCSC page; correct, do not
+  change); TEST→GND, AGND→GND.
 - **EEPROM 93LC46B (U7)**: interface **was wrong** (DO+DI both direct to
   EEDATA) → fixed per DS Table 3.4: EE_DO net, R30 2.2k (C25879) to EE_DATA,
   R31 10k (C25744) pull-up to 3V3, DI direct. 93LC46B = fixed 16-bit org =
   correct for FT2232H. Verified in netlist.
+- **EE_CS pull-down (R43, 10 kΩ) — ADDED 2026-07-31.** FT2232H DS Table 3.4
+  states EECS/EECLK/EEDATA are all **"Tri-State during device reset"**, so CS
+  floats while the FT2232H is in reset. The Microchip 93LC46B DS is explicit:
+  *"an external 10 kΩ pull-down protection resistor should be added to the CS
+  pin"*, and **CS is active-HIGH** (*"A high level selects the device; a low
+  level deselects the device and forces it into Standby mode"*). **It must be
+  a pull-DOWN — a pull-UP would hold the EEPROM permanently selected.** Netlist
+  verified: `EE_CS: R43.1, U7.1, U8.63`.
+- **EE_CLK deliberately has NO pull resistor — do not add one.** With CS held
+  low the device is in Standby, and the 93LC46B DS states *"Before a Start
+  condition is detected, CS, CLK and DI may change in any combination…
+  without resulting in any device operation."* A floating clock is harmless
+  once CS is pulled down. (A reviewer suggested pull-ups on both EE_CLK and
+  EE_CS; only the CS pull-DOWN is correct.)
+- **FT2232H oscillator needs no RExt / no external feedback resistor —
+  settled, do not add one.** DS Figure 6.5 shows crystal + 2 caps only; FTDI
+  publishes **no gm, no drive-level and no negative-resistance figure**, so a
+  drive resistor cannot be sized from their data and their reference does not
+  use one (feedback is internal). This is a genuine architectural difference
+  from the W5100S, which explicitly has *no* internal feedback resistor and
+  models RExt in its Figure 23. Y1 caps stay 18 pF (CL=12 pF part).
 - **FTDI↔flash/FPGA config pins**: **rewired 2026-07-18** to stock iceprog
   convention: SCK=ADBUS0, MOSI=ADBUS1, MISO=ADBUS2, FLASH_CS=ADBUS4,
   CDONE=ADBUS6, CRESET=ADBUS7 (verified against iceprog.c; old ADBUS3/ACBUS0/
@@ -116,8 +138,78 @@ datasheet extraction, WebSearch/WebFetch for parts and reference designs.
   itself uses 12k+300R; 0.8 % immaterial). Closed.
 - **Crystal Y2**: 25 MHz, CL=12 pF part (C9006) vs 18 pF caps → CL≈12 pF ✓
   (DS Table 9 wants 12 pF); mandatory external 1 MΩ feedback (R17) present ✓
-  (DS: "W5100S has no feedback resistor"). FTDI ref-note: no series RExt
-  (ref uses 0 Ω) — accepted.
+  (DS: "W5100S has no feedback resistor"). **The caps are CORRECT: both
+  crystals are CL = 12 pF, and `CL = C/2 + Cstray` → 18 pF caps deliver
+  exactly 12 pF. An attempt on 2026-07-31 to "fix" the caps to 30 pF/10 pF
+  was a regression against this reviewed item and has been reverted. Do not
+  change the crystal caps.** The trigger for that mistake was wrong `CL`
+  metadata in the schematic symbol properties (Y1 said 18 pF, Y2 said 8 pF) —
+  those properties have now been corrected to match the parts (see below).
+
+  ⚠️ **Where the CL = 12 pF figure actually comes from — read this before
+  "re-verifying" it.** It is NOT in `datasheets/Ysx321SL.pdf`. That is the
+  generic YSX321SL *series* datasheet and its Load Capacitance row reads
+  **"10pF, 20pF, or specify"** — so opening it and looking for 12 pF gives
+  the alarming impression that the fitted caps are wrong for either standard
+  option. These two parts are the "or specify" variants, and CL is fixed by
+  the **ordering code**, confirmed on the LCSC part pages (re-confirmed
+  2026-07-31):
+    - Y1 `X322512MOB4SI` (**C70565**): 12 MHz, **CL 12 pF**, ±10 ppm, ESR 80 Ω
+    - Y2 `X322525MOB4SI` (**C9006**):  25 MHz, **CL 12 pF**, ±10 ppm, ESR 50 Ω
+  Everything else in the series datasheet *does* corroborate the review
+  numbers used elsewhere in this file: C0 = 3 pF max, DL = 200 µW max
+  (100 µW typ — the basis for the R44 RExt decision), and the ESR bands
+  (12–15 MHz → 80 Ω, 16–31 MHz → 50 Ω). Only CL needs the part page.
+
+  **The common way to get this wrong** is to apply `C = 2 × CL` = 24 pF and
+  conclude 18 pF is too small. That omits stray capacitance. The correct
+  form is `C = 2 × (CL − Cstray)` = 2 × (12 − 3) = **18 pF**, where Cstray
+  (PCB trace + oscillator pin capacitance) is ~3 pF. If a reviewer says the
+  caps are low, check whether they subtracted Cstray before re-opening this.
+
+  **Residual sensitivity (the real uncertainty, and it is acceptable):** the
+  match is exact only if Cstray is exactly 3 pF; the realistic range is
+  2–5 pF, giving CL_actual 11–14 pF against the rated 12 pF. Pulling with
+  C0 = 3 pF and motional C1 ≈ 6 fF works out to roughly **+14 ppm to
+  −24 ppm**. Against 100BASE-TX's ±100 ppm requirement on the 25 MHz
+  reference, the worst-case stack (±10 tolerance + ±20 temp + ±3/yr aging +
+  ±24 load) is ~±60 ppm — inside spec with margin. For Y1 the FT2232H's USB
+  budget (±500 ppm high-speed, ±2500 ppm full-speed) is met by a wide
+  margin. No change warranted; measure at bring-up if convenient.
+- **RExt on XTAL_O (R44, 49.9 Ω) — ADDED 2026-07-31, reverses the earlier
+  "no series RExt (ref uses 0 Ω) — accepted" decision.** New evidence that
+  was not available at the original review: the crystal datasheet only
+  entered the repo on 2026-07-31 and rates the part at **DL = 200 µW max**
+  (100 µW typ), whereas W5100S Table 9 tells you to select a crystal rated
+  **500 µW** — i.e. the fitted crystal can be overdriven ~2.5× by the chip.
+  RExt is the datasheet's own prescribed remedy ("RExt: Resistor for
+  limiting the drive level (DL)… Excess power can destroy the crystal") and
+  is modelled in DS Figure 23. Topology follows Figure 23 exactly — RF
+  (R17) across the **chip pins** XSCI↔XSCO, RExt between XSCO and the
+  crystal/CL2 node; this required splitting the old XTAL_O net, so U11 pin 11
+  now sits on a new **XSCO** net:
+      XTAL_I : C62(CL1), R17(RF), U11.12, Y2.1
+      XSCO   : R17(RF),  R44(RExt), U11.11
+      XTAL_O : C63(CL2), R44(RExt), Y2.3
+  Value 49.9 Ω chosen from the DS gain-margin formula with the REAL specs
+  (F=25 MHz, ESR=50 Ω per the 16–31 MHz band, C0=3 pF max, CL=12 pF,
+  gm=16.7 mA/V): **margin 7.53×**, against a DS requirement of ≥5 (the
+  "6.99 dB" in Table 8 is 10·log₁₀5). **Ceiling is 100 Ω** — 120 Ω already
+  fails the startup spec. Fitted value is a starting point; part fields are
+  intentionally blank so it is re-selected/confirmed at bring-up by
+  measuring drive level.
+- **Crystal symbol properties corrected 2026-07-31** (they were metadata-only
+  errors, no copper impact, but they caused the regression above):
+  Y1 CL 18 pF→**12 pF**, ESR 50 Ω→**80 Ω** (DS band 12–15 MHz),
+  tol ±30 ppm→**±10 ppm**; Y2 CL 8 pF→**12 pF**, C0 7 pF→**3 pF**,
+  ESR 30 Ω→**50 Ω** (band 16–31 MHz), tol ±50 ppm→**±10 ppm**.
+- **Known deviation, accepted**: W5100S DS **Table 8 specifies a CL = 8 pF
+  crystal** (revision history logs "Modified Load capacitance value
+  (12p → 8p)"), while **Table 9 still says 12 pF** and was never updated.
+  The fitted part is 12 pF, matching Table 9. Frequency accuracy is
+  unaffected (the crystal sees exactly its rated load, so no pulling error);
+  the only cost is gain margin, which is 7.75× with R44 — well clear of the
+  ≥5 requirement. Accepted; do not re-flag without bench evidence.
 - **MDI section — now implements the WIZnet ref schematic item-for-item**:
   49.9 Ω×4 (R26–R29, C25120) + 100 nF×2 (C18/C19) termination on the PHY-side
   nets; 3.3 Ω×4 series dampers (R32–R35, C137986) — chain per line:
@@ -164,10 +256,83 @@ datasheet extraction, WebSearch/WebFetch for parts and reference designs.
   rated for 3.3 V lines. Note: BOM part C49383400 is the **ElecSuper clone**
   ("(ES)"), pin-compatible — bring-up suspect only if ESD behaviour odd.
 - **EXTIN**: 10k (R18) to **SP1_3V3 (the GC's own rail)** — correct, doesn't
-  back-power. **12 V**: J3.5 → 12V_EXI (power tree). J3.8 (second 3.3 V pin)
-  deliberately NC. Series elements: R24 100 Ω on EXI_CLK (input damping),
-  R21/R25 as above. INT (J3.3) driven by FPGA pin 46 — gateware should use
-  open-drain emulation (TODO).
+  back-power. **12 V**: J3.5 → **12V_RAW → U13 eFuse → 12V_EXI** (see next
+  bullet; was a straight J3.5→12V_EXI connection before 2026-07-31). J3.8
+  (second 3.3 V pin) deliberately NC. Series elements: R24 100 Ω on EXI_CLK
+  (input damping), R21/R25 as above. INT (J3.3) driven by FPGA pin 46 —
+  gateware should use open-drain emulation (TODO).
+- **12 V inrush limiter (U13, TPS25961 eFuse) — ADDED 2026-07-31** to protect
+  the GameCube's 12 V supply from the surge charging C65+C3+C4+C6 (**120 µF**)
+  at plug-in/power-on. Topology (netlist-verified):
+      12V_RAW  : J3.5, D3(TVS), C66(Cin 100nF), R46, U13.6 IN
+      12V_EXI  : U13.1 OUT, C65, C3, C4, C6, U3.3 VIN, U3.5 EN
+      EFUSE_EN : R46, R47, U13.5 EN/UVLO
+      EFUSE_ILIM: R45, U13.3 ILIM
+      GND      : U13.2 OVLO, U13.4 GND, R45.2, R47.2, C66.2
+  **D3 (SMAJ12A TVS) stays on the INPUT side on purpose** — it clamps
+  GC-side surges before they reach the eFuse's 21 V absolute maximum. **C65
+  is on the OUTPUT side on purpose** — it is the bulk cap whose inrush we are
+  rate-limiting; moving it upstream would defeat the whole circuit.
+  **U3 (buck) needed no change**: because the eFuse was inserted *upstream of
+  the existing 12V_EXI net name*, U3's VIN and EN both land on the switched
+  rail automatically.
+  - **Inrush is set by the device's INTERNAL slew rate, not an external cap.**
+    dV/dt = 5.17 V/ms (fixed, typical) ⇒ I = C·dV/dt = 120 µF × 5.17 V/ms =
+    **621 mA** over a 2.3 ms ramp. R_ILIM only matters if it is set *below*
+    that figure.
+  - **R45 = 100 kΩ ⇒ I_LIM ≈ 500 mA** (datasheet Equation 6: R_ILIM =
+    50000/I_LIM; 100 kΩ is one of TI's own characterised points, 0.516 A typ,
+    ±18% ⇒ 0.42–0.61 A). This both caps inrush at 500 mA and gives **3.8×
+    headroom** over the ~130 mA steady-state 12 V draw. 100 kΩ is deliberately
+    inside a valid ON-resistance bin — **Table 7-1 forbids 58.8–66.7 kΩ,
+    111–142 kΩ and 250–500 kΩ**; do not "round" R45 into those bands.
+  - **Startup dissipation is safe**: FET energy = ½CV² = **8.65 mJ** regardless
+    of ramp rate ⇒ ~3.0 W average over 2.9 ms. Figure 6-31 puts time-to-thermal-
+    shutdown at ~3 W far beyond 100 ms. Steady-state loss is 106 mΩ × 0.13² =
+    **1.8 mW**, negligible.
+  - **R46/R47 = 620 k/100 k ⇒ UVLO on at 8.9 V typ (9.2 V worst case), off at
+    8.2 V**, 16.7 µA leakage. **This is deliberately well below 12 V — do not
+    "improve" it upward.** Two reasons: (a) the EN/UVLO threshold is specified
+    1.2–1.28 V, so an ~11.4 V setting has a worst case of 11.78 V and could
+    refuse to start on a healthy console once PSU tolerance is added; (b) more
+    importantly the falling threshold scales with it (91% of rising), and the
+    eFuse pulls 500 mA during the 2.9 ms ramp — at a ~11 V setting a source
+    impedance of only ~1.2 Ω would sag the rail below drop-out mid-ramp,
+    causing retry oscillation that may never complete startup. The 620 k/100 k
+    setting tolerates **3.85 V of sag**. If tighter supervision is ever wanted,
+    680 k/100 k (9.7 V on, 3.2 V sag margin) is the furthest to push it —
+    beyond that use an FPGA-read divider, not the eFuse enable.
+  - **OVLO tied directly to GND** = internal fixed OV threshold. Note the OVLO
+    pin's absolute maximum is only **6.5 V** — it must never see the 12 V rail.
+  - **Thermal pad must connect to the GND plane** (datasheet requirement); the
+    chosen footprint is the `_ThermalVias` variant for this reason.
+  - Symbol: no TPS25961 exists in the KiCad libraries (the stock `TPS2596xx`
+    is an 8-pin SO-8 with a different pinout — do not substitute it), so
+    `hardware/TPS25961.kicad_sym` was created and registered in
+    `sym-lib-table`. Footprint `Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm_ThermalVias`.
+- **EXI series-resistor assignment — VERIFIED AGAIN 2026-07-31 against the
+  netlist + gateware pin directions, do not swap.** The DO/DI fix above moved
+  the *driven* line from J3.6 to J3.9, and the R21/R25 identities were swapped
+  to follow it. Confirmed live:
+      EXI_MISO : U9.3 (synth.py dir="o", FPGA drives) -> R25 33 Ω -> J3.9 (DI)
+      EXI_MOSI : J3.6 (DO, GC drives) -> R21 22 Ω -> U9.4 (dir="i", FPGA rx)
+  **33 Ω belongs on MISO** because that is the only line this board drives, so
+  it is genuine source termination (33 Ω + ~30 Ω iCE40 output ≈ 60 Ω into a
+  ~50 Ω trace — mildly over-damped, the safe direction for EMI on a short
+  run). **22 Ω belongs on MOSI**, where the GC is the driver at the far side
+  of a connector we do not control; source termination is impossible there, so
+  the resistor only limits clamp current and damps at the receiver, a role
+  where the exact value matters much less. Swapping them would under-terminate
+  the one line we actually drive. This is the exact trap a future reader may
+  fall into after seeing the console-perspective DO/DI naming — the values
+  are already on the correct lines.
+- **CS deliberately has NO series resistor — known asymmetry, not an
+  oversight.** All three of EXI_CLK, EXI_MOSI and EXI_CS are GC-driven inputs,
+  but only CLK (R24 100 Ω) and MOSI (R21 22 Ω) carry damping; J3.10 goes
+  straight to U9.45. CS is essentially static within a transaction (it frames
+  the transfer rather than toggling per bit), so receiver ringing matters far
+  less than on the clock or data lines. Recorded so it is not "fixed" on the
+  assumption it was forgotten; add one only if bring-up shows CS-edge noise.
 - **J3 footprint provenance**: 12 contacts, 1 mm effective pitch, two
   staggered depth rows, **front side only**, fingers to the board edge (the
   `.kicad_dru` has a J3 edge-clearance exception for this). Geometry comes