Add REVIEW.md: complete hardware-review coverage record

Documents everything examined in the 2026-07-17/18 review - not just
findings but full coverage with verdicts, so future sessions know what
not to re-review: per-sheet verification against datasheets and the
WIZnet reference design, the settled look-wrong-but-correct list
(VPHY/VPLL on 3.3V, D4/D5 floating VBUS + flow-through, EN at 12V,
RSET 12.4k, no CT cap, DO/DI direction evidence), PCB/JLC/BOM audit
state, explicit not-reviewed list (bench/gateware items), and a binding
rule to keep the file updated in the same commit as any change to a
reviewed circuit. Referenced from CLAUDE.md alongside TODO.md.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

CLAUDE.md

@@ -254,13 +254,21 @@ plug (schematic, PCB, custom GameCube symbol library). Used to verify pad geomet
 before ordering the interposer PCB; not part of the FPGA build.
 
 `hardware/re-bba-rb/` — the actual adapter PCB (FT2232H + iCE40UP5K + W5100S,
-powered from SP1 12 V via buck). **Open findings from the 2026-07-17 hardware
-review live in `hardware/re-bba-rb/TODO.md`** — read it before editing the
-schematics, ordering boards, or writing the board PCF. Highlights: the W5100S
-MDI 49.9 Ω termination network is missing; the FTDI EEPROM needs its 2.2 k/10 k
-resistors; stock iceprog doesn't match the FTDI pin mapping. (The EXI DO/DI
-swap found in the review is FIXED — SP1 naming is console-perspective, DO = GC→
-adapter = MOSI; board pin map: EXI_MOSI = FPGA pin 4, EXI_MISO = pin 3.)
+powered from SP1 12 V via buck). Two companion documents, both mandatory
+reading before touching this board:
+- **`hardware/re-bba-rb/TODO.md`** — open action items (what still needs doing:
+  PCB placement of the 2026-07-18 fix parts, board PCF, bench checks, JLC
+  ordering options).
+- **`hardware/re-bba-rb/REVIEW.md`** — the review **coverage record**: every
+  circuit that has been verified against its datasheet/reference design, with
+  verdicts — including things that LOOK wrong but are settled-correct (FT2232H
+  VPHY/VPLL on 3.3 V; D4/D5 floating VBUS + split-net flow-through; TPS562201
+  EN at 12 V; RSET 12.4 k; no TPS22810 CT cap; SP1 DO = GC→adapter = MOSI).
+  **Do not re-review or "fix" anything listed there without new evidence, and
+  keep REVIEW.md updated in the same commit whenever a reviewed circuit
+  changes or a new review is performed.**
+The authoritative board pin map (EXI, ETH bus, UART crossover, LED/DBG pins)
+is in both files; use it when writing the board PCF.
 
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