Roflin
a86aa255f1
Documents everything examined in the 2026-07-17/18 review - not just findings but full coverage with verdicts, so future sessions know what not to re-review: per-sheet verification against datasheets and the WIZnet reference design, the settled look-wrong-but-correct list (VPHY/VPLL on 3.3V, D4/D5 floating VBUS + flow-through, EN at 12V, RSET 12.4k, no CT cap, DO/DI direction evidence), PCB/JLC/BOM audit state, explicit not-reviewed list (bench/gateware items), and a binding rule to keep the file updated in the same commit as any change to a reviewed circuit. Referenced from CLAUDE.md alongside TODO.md. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>