Close out functional/robustness findings: iceprog rewire, PR1, ETH_RST, debug provisions
Schematic fixes (PCB placement/routing of new parts pending, F8 lists them): - FTDI rewired to stock iceprog convention: FLASH_CS ADBUS3->ADBUS4, CDONE ACBUS1->ADBUS6, CRESET ACBUS0->ADBUS7 (old pins NC). With a blank 93LC46B (default 0403:6010) stock iceprog now works unmodified; EEPROM workflow decided: ship blank, FT_PROG optional (keep VID/PID). - TPS2116 PR1 divider: R3 200k->150k (C25755) - switchover now at 2.30-2.70V worst case instead of 20mV under the 3.3V rail. - ETH_RST: R36 10k pull-up to ETH_3V3 (RSTn floats during FPGA config). - Debug provisions: D6 green heartbeat LED (C72043) on FPGA pin 47, D7 red EXI-activity LED (C2286) on pin 48, 330R C25104 series; J4 6-pin LA header (GND + DBG0-4 = pins 9/10/11/12/6, unpopulated); TP1-TP5 test points (3V3/1V2/ETH_3V3/GC_ON/GND, in_bom no); FID1-3 fiducials placed board-only on the PCB, track-clearance checked. - Embedded Device:LED / Connector:TestPoint / Conn_01x06 lib symbols. Closed by analysis (no change): TPS22810 CT cap unnecessary (DS Table 2: ~98us rise at 3.3V with CT=0 -> ~0.5A inrush); RSET_BG 12.4k accepted (12.3k is E192; WIZnet ref synthesizes it as 12k+300R; 0.8% immaterial). Verified: ERC 0; netlist 132 vs BOM 125 differing only by the 7 deliberate in_bom=no items (J3, J4, TP1-5); LED polarity and TP rails confirmed in netlist; PCB DRC 0 errors with fiducials placed. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
This commit is contained in:
+2139
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@@ -2588,7 +2588,7 @@
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(justify left)
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)
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)
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(property "Value" "200k"
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(property "Value" "150k"
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(at 83.566 29.21 0)
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(show_name no)
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(do_not_autoplace no)
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@@ -2632,7 +2632,7 @@
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)
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)
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)
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(property "MPN" "0402WGF2003TCE"
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(property "MPN" "0402WGF1503TCE"
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(at 0 0 0)
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(hide yes)
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(show_name no)
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@@ -2654,7 +2654,7 @@
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)
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)
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)
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(property "LCSC" "C25764"
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(property "LCSC" "C25755"
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(at 0 0 0)
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(hide yes)
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(show_name no)
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+60
-34
@@ -72,15 +72,19 @@ remaining work is the Functional/Broader/ordering lists below.
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## Functional / robustness
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- [ ] **iceprog pin mismatch**: iceprog hardcodes CS=ADBUS4, CDONE=ADBUS6,
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CRESET=ADBUS7. Board uses FLASH_CS=ADBUS3, CDONE=ACBUS1, CRESET=ACBUS0.
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Rewire to the iCEbreaker convention, or maintain a patched iceprog.
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- [ ] **TPS2116 PR1 divider margin**: 200k/100k gives PR1 = 1.10 V vs
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VREF = 1.0 V ±8 % (max 1.08 V) — 20 mV worst-case margin against the
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3.3 V buck output. Change R3 to 150 k → switchover at 2.30–2.70 V.
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- [ ] **ETH_RST pull-up**: W5100S RSTn is a plain input (no internal pull) and
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floats while the FPGA configures. Add 10 k to **ETH_3V3** (not 3V3, so
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it sits low when the ETH rail is off).
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- [ ] **iceprog pin mismatch — schematic FIXED 2026-07-18**: FLASH_CS moved
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ADBUS3→ADBUS4 (U8 pin 21), CDONE ACBUS1→ADBUS6 (pin 23), CRESET
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ACBUS0→ADBUS7 (pin 24) — now exactly stock iceprog / iCEbreaker
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channel-A convention; old pins are NC. Pull-ups R11/R12 unchanged.
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- [ ] PCB: reroute the three lines to the new U8 pins (F8 shows the
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pad-net changes).
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- [x] **TPS2116 PR1 divider margin — FIXED 2026-07-18**: R3 200k→150k
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(0402WGF1503TCE, LCSC C25755). PR1 = 1.32 V nominal; switchover at
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GC_3V3 = 2.30–2.70 V worst-case — safely below the 3.3 V rail. (Value
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change only, same footprint — no PCB work.)
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- [ ] **ETH_RST pull-up — schematic FIXED 2026-07-18**: R36 10 k (C25744)
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from ETH_RST to **ETH_3V3** (low when ETH rail off).
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- [ ] PCB: place/route R36 near U11 pin 48.
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- [ ] **Gateware: gate all outputs on GC_ON** — when GC_ON=0 the W5100S is
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unpowered (U12) and the GC is off, but FPGA banks stay at 3.3 V. Hold
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the W5100S bus and EXI outputs Hi-Z/low to avoid back-powering.
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@@ -93,23 +97,37 @@ remaining work is the Functional/Broader/ordering lists below.
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## Broader items (beyond the wiring review — block fab on the first two)
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- [ ] **Write the re-bba-rb pin constraints** — `exi_bba/synth.py` still targets
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the iCEbreaker. This board: EXI on FPGA pins 3 (IOB_9b), 4 (IOB_8a),
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44 (EXI_CLK, G6), 45 (EXI_CS), 46 (EXI_INT); W5100S bus on the IOT bank
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(23–43); CLK12 on 20 (G3); GC_ON on 21; ETH_RST on 2; UART on 18/19.
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This is where the DO/DI swap and the UART crossover (UART_TXD = FTDI
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output = FPGA RX) get resolved. Pure software; do it before ordering to
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prove the pinout.
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- [ ] **Add debug provisions — the board currently has none.** RGB0–2 are
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unconnected, no LEDs, no button, no test points; the CLAUDE.md bring-up
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plan (StatusPanel heartbeat/activity LEDs + BTN re-init) has nothing to
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drive. Spare IOBs: 6, 9, 10, 11, 12, 13, 47, 48. Add ≥2 LEDs (heartbeat,
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EXI activity), a 4–6 pin debug header (logic-analyzer access — EXI
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CLK/CS/MOSI/MISO are what you probe when enumeration fails), and test
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points on 3V3 / 1V2 / ETH_3V3 / GC_ON. Cannot be retrofitted.
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- [ ] **Verify mechanical fit** — outline + finger geometry vs SP1ETH/ETH2SP1
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references (per CLAUDE.md), RJ45 and USB-C protrusion vs the GC serial
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port bay opening. An earlier commit says "need to remeasure PCB outline";
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sp1_test_plug validates pads only, not the envelope.
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the iCEbreaker. Full board pin map: EXI_MOSI = 4 (IOB_8a, in),
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EXI_MISO = 3 (IOB_9b, out), EXI_CLK = 44 (G6), EXI_CS = 45,
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EXI_INT = 46; W5100S bus on the IOT bank (23–43); CLK12 = 20 (G3);
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GC_ON = 21; ETH_RST = 2; UART: FPGA RX = 18 (net UART_TXD!, FTDI
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output), FPGA TX = 19; **debug: LED_G = 47 (heartbeat), LED_R = 48
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(EXI activity), DBG0–4 = 9/10/11/12/6 (J4 header)**. Pure software;
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do before ordering to prove the pinout.
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- [ ] **Debug provisions — schematic DONE 2026-07-18** (was: board had none):
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- D6 green heartbeat LED (Everlight 19-217/GHC-YR1S2/3T, C72043,
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Basic) on FPGA pin 47 (LED_G) via R37 330 Ω (C25104);
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- D7 red EXI-activity LED (KENTO KT-0603R, C2286, Basic) on pin 48
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(LED_R) via R38;
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- J4 6-pin debug header (unpopulated, in_bom no): GND + DBG0–4 =
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FPGA pins 9/10/11/12/6 — route EXI CLK/CS/MOSI/MISO copies here in
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gateware for logic-analyzer bring-up;
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- TP1 3V3, TP2 1V2, TP3 ETH_3V3 (ethernet sheet), TP4 GC_ON, TP5 GND
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(1.5 mm pads, in_bom no);
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- FID1–3 fiducials placed directly on the PCB (board-only) at
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(195, 68.5)/(131, 48)/(163, 44.5) — copper-clear, DRC 0.
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- [ ] PCB: place/route the 11 schematic footprints (D6/D7, R36/R37/
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R38, TP1–5, J4) — F8 pulls them in. LEDs need visibility with
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the GC shell on: place near the RJ45/USB edge if possible.
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- [ ] **Verify mechanical fit** (bench item — cannot be verified in repo):
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outline vs the SP1 slot, RJ45/USB-C protrusion vs the GC serial port
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bay opening. An earlier commit says "need to remeasure PCB outline".
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Note 2026-07-18: the J3 footprint (12 contacts, 1 mm effective pitch,
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two staggered depth rows, front-side only, fingers to the board edge
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per the .kicad_dru exception) is the geometry derived from the
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physical sp1_test_plug iterations — the test-plug project itself
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contains no reusable finger footprint to diff against, so the
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provenance is the physical test, not a file comparison.
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- [x] **SP1 12 V rail viability — VERIFIED against existing projects
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(2026-07-17).** webhdx's IDE-EXI v2 for Serial Port 1 (which became the
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commercial M.2 Loader): "New switching power regulator supplies 3.3V@2A
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@@ -123,10 +141,12 @@ remaining work is the Functional/Broader/ordering lists below.
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12 V unused (runs from the 3.3 V pins). Remaining bench check only:
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- [ ] inrush into C65 (100 µF) + 2×10 µF buck input caps at GC power-on
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(the M.2 Loader precedent suggests this is a non-issue).
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- [ ] **Decide FT2232H EEPROM contents + flashing workflow** — blank 93LC46B
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enumerates with default VID/PID (works, generic); custom
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VID/PID/serial/product string needs FT_PROG provisioning. Tied to the
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iceprog-pin-mapping decision above (changes the schematic).
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- [x] **FT2232H EEPROM contents + flashing workflow — DECIDED 2026-07-18**:
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ship with a **blank** 93LC46B. FT2232H falls back to its default
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config (VID 0403 / PID 6010, dual channel, MPSSE on channel A) —
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exactly what stock iceprog opens by default, which now matches the
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rewired pins. Optionally program serial/product string later with
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FT_PROG (do NOT change VID/PID, or iceprog needs -d vid:pid).
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- [ ] CC1/CC2 have no ESD protection (USBLC6 covers D+/D− only) — optional,
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most hobby designs skip; note spare-channel budget if respinning D2 area.
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- [x] `.history/` (embedded `.git`) — VERIFIED ignored via root
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@@ -134,8 +154,11 @@ remaining work is the Functional/Broader/ordering lists below.
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## Minor / BOM
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- [ ] RSET_BG: datasheet says 12.3 kΩ 1 % (ref schematic: 12 k + 300 Ω);
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board has 12.4 k (~0.8 % off). Match if convenient.
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- [x] RSET_BG 12.4 k — ACCEPTED 2026-07-18 (closed, no change): datasheet
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says 12.3 kΩ, but that is an E192 value with no JLC Basic part —
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WIZnet's own reference synthesizes it as 12 k + 300 Ω. The 0.8 %
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deviation on a bandgap bias resistor is immaterial (well under the
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combined tolerance of the ref design's two 1 % parts).
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- [x] Crystals Y1/Y2 — VERIFIED 2026-07-17: the BOM parts are both CL = 12 pF
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(Y1 YXC X322512MOB4SI / C70565, Y2 X322525MOB4SI / C9006, both JLC
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Basic, ±10 ppm) — correct for the 18 pF load caps and the W5100S
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@@ -144,8 +167,11 @@ remaining work is the Functional/Broader/ordering lists below.
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C6 50 V, C65 25 V (Lelon SMD electrolytic); D3 SMAJ12A correct.
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- [x] 1 % tolerance — VERIFIED in BOM audit 2026-07-17: R1/R2, R3/R4, R10,
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R16 are all 1 % UNI-ROYAL parts (and new R26–R35 are 1 %).
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- [ ] TPS22810 CT: floating = fastest ramp (~0.7 A inrush into ETH rail
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caps). Consider CT = 10 nF footprint (DNP-able).
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- [x] TPS22810 CT — NOT NEEDED 2026-07-18 (closed, no change): datasheet
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Table 2 shows the internal ramp dominates at low VIN — rise time at
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VIN = 3.3 V is ~98 µs even with CT = 0 (vs 102 µs at CT = 1 nF).
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Inrush ≈ 15 µF × 3.3 V / 98 µs ≈ 0.5 A for <100 µs — trivial for the
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2 A buck. A CT cap would buy nothing measurable.
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- [ ] Verify HR911105A internal LED pinout (assumed: 9/12 anodes via
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R14/R15 330 Ω to ETH_3V3, 10/11 cathodes to LNKn/ACTn) and the
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Bob-Smith common on pin 8 (tied straight to GND here; WIZnet ref
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@@ -4096,10 +4096,6 @@
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(at 276.86 163.83)
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(uuid "1d32d965-50db-4ea3-ac37-eff00240d6c8")
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(no_connect
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(uuid "1f0b71fa-6308-4ac1-9492-c9ba20cab6de")
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@@ -4180,14 +4176,6 @@
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(at 276.86 133.35)
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(uuid "d4d6bdc8-1cd8-4c3b-8f3c-d7b7d09b42cc")
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(at 276.86 100.33)
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(uuid "e1e2ed38-79ca-478c-9ef4-aea660fe4a36")
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)
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||||
(no_connect
|
||||
(at 276.86 92.71)
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||||
(uuid "e3816d9e-97cc-4a5e-a385-6e8cb45d3d9f")
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||||
)
|
||||
(no_connect
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||||
(at 276.86 120.65)
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||||
(uuid "f250de11-3d72-4ddb-8a0f-5f79eae94b40")
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||||
@@ -5846,7 +5834,7 @@
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)
|
||||
(hierarchical_label "CRESET"
|
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(shape bidirectional)
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(at 276.86 105.41 0)
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(at 276.86 100.33 0)
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(effects
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@@ -5879,7 +5867,7 @@
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)
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||||
(hierarchical_label "CDONE"
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(shape bidirectional)
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(at 276.86 107.95 0)
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(at 276.86 97.79 0)
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(effects
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@@ -5978,7 +5966,7 @@
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)
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(hierarchical_label "FLASH_CS"
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(shape bidirectional)
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||||
(at 276.86 90.17 0)
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(at 276.86 92.71 0)
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@@ -13488,4 +13476,16 @@
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(page "1")
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||||
(no_connect
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||||
(at 276.86 90.17)
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||||
)
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||||
(no_connect
|
||||
(at 276.86 105.41)
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||||
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||||
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||||
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)
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)
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@@ -6517,6 +6517,130 @@
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)
|
||||
(embedded_fonts no)
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)
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||||
|
||||
(symbol "Connector:TestPoint"
|
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(pin_numbers
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(hide yes)
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)
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||||
(pin_names
|
||||
(offset 0.762)
|
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(hide yes)
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)
|
||||
(exclude_from_sim no)
|
||||
(in_bom yes)
|
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(on_board yes)
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(in_pos_files yes)
|
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(duplicate_pin_numbers_are_jumpers no)
|
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(property "Reference" "TP"
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(at 0 6.858 0)
|
||||
(show_name no)
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||||
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(property "Footprint" ""
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(property "Datasheet" ""
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||||
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||||
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||||
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||||
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||||
(property "ki_fp_filters" "Pin* Test*"
|
||||
(at 0 0 0)
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||||
(show_name no)
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||||
(do_not_autoplace no)
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||||
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|
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||||
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|
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|
||||
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||||
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(symbol "TestPoint_1_1"
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(pin passive line
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||||
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||||
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|
||||
(embedded_fonts no)
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||||
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||||
)
|
||||
(junction
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||||
(at 167.64 81.28)
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@@ -15981,4 +16105,278 @@
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)
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)
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||||
)
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||||
(text "W5100S RSTn pull-up: RSTn is a plain\ninput (no internal pull) and floats while\nthe FPGA configures. Pulled to ETH_3V3\n(not 3V3) so it is low when ETH rail off."
|
||||
(exclude_from_sim no)
|
||||
(at 254.0 95.25 0)
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(effects
|
||||
(font
|
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Reference in New Issue
Block a user