TODO: verify and update status - all critical findings resolved
Re-verified every open item against the current board: - All three critical findings (DO/DI swap, MDI termination incl. dampers + center-tap bypass, FTDI EEPROM resistors) now done in both schematic and PCB - marked resolved with review results - Marked verified-done: 12V cap ratings, 1% tolerances, .history ignore, fiducial check (absent - to add with debug pass) - Confirmed still open: ETH_RST pull-up, PR1 divider margin (R3 still 200k), RSET 12.4k vs 12.3k, TPS22810 CT, iceprog pin mapping, board PCF, debug LEDs/test points, mechanical fit, ordering options Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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# re-bba-rb board — open items from hardware review (2026-07-17)
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Full review of schematics + PCB against component datasheets
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(`datasheets/` — restore from commit `db457a0`, see Housekeeping), the WIZnet
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W5100S reference schematic, and JLCPCB manufacturing limits. ERC/DRC: clean.
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Full review of schematics + PCB against component datasheets (in
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`datasheets/`), the WIZnet W5100S reference schematic, and JLCPCB
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manufacturing limits. Status 2026-07-18: **all three critical findings fixed
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in schematic AND PCB** (ERC 0, DRC 0 errors / 0 unconnected / 0 parity);
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remaining work is the Functional/Broader/ordering lists below.
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## Critical — must fix before (or with) next fab
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## Critical — ALL RESOLVED (schematic + PCB, verified 2026-07-18)
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- [x] **EXI DO/DI swapped at J3 — FIXED 2026-07-17** (all copper unchanged).
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YAGCD SP1 naming is console-perspective: pin 6 `DO` = GC data **out** →
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@@ -25,8 +27,8 @@ W5100S reference schematic, and JLCPCB manufacturing limits. ERC/DRC: clean.
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- [ ] Use this final pin map when writing the board PCF (see Broader
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items): MOSI = pin 4, MISO = pin 3, CLK = 44 (G6), CS = 45,
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INT = 46.
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- [ ] **W5100S MDI termination network** (`ethernet.kicad_sch`) — schematic
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part DONE 2026-07-17: added R26/R27 (49.9 Ω 1%, LCSC C25120) from
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- [x] **W5100S MDI termination network — DONE (schematic + PCB)**: added
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R26/R27 (49.9 Ω 1%, LCSC C25120) from
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TXOP/TXON to a common node + C18 (100 nF) to GND, and R28/R29 + C19 for
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RXIP/RXIN, on the PHY-side nets per the WIZnet reference schematic.
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ERC 0; netlist verified. PCB rework REVIEWED 2026-07-18 — PASS:
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@@ -38,17 +40,16 @@ W5100S reference schematic, and JLCPCB manufacturing limits. ERC/DRC: clean.
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- [x] D4/D5 flow-through verified pad-by-pad (PHY side faces U11,
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cable side faces J2); In1 plane correctly voided under the
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magjack's cable/isolation side, all layers clear there.
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- [ ] 3.3 Ω series dampers (WIZnet note 6) — schematic ADDED
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2026-07-18: R32–R35 (YAGEO RC0402FR-073R3L, LCSC C137986) in
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line U11→transformer; chip-side nets stay PHY_*, D4/D5-side
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renamed MDI_* (netclass patterns added to ETH_DP in .kicad_pro
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so the impedance rules still police both halves). PCB: cut the
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four lines between the termination cluster and D4/D5 and insert
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the footprints there (F8 pulls them + the MDI_* pad renames).
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- [ ] Center-tap bypass (WIZnet note 7) — schematic ADDED 2026-07-18:
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C20 100 nF (C1525) + C21 1 µF 0603 (C15849) on ETH_3V3. PCB:
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place BOTH right at J2 pins 4/5, tapping the In2 ETH_3V3 island
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with short traces + local GND vias.
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- [x] 3.3 Ω series dampers (WIZnet note 6) — DONE 2026-07-18: R32–R35
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(YAGEO RC0402FR-073R3L, LCSC C137986) in line U11→transformer;
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chip-side nets stay PHY_*, D4/D5-side renamed MDI_* (patterns
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added to ETH_DP netclass in .kicad_pro). Inserted in-line on the
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PCB, each in its own line row; MDI_* stubs 1.45–1.48 mm, no new
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vias; pair skew after insertion TX 0.66 mm / RX 1.81 mm (fine).
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- [x] Center-tap bypass (WIZnet note 7) — DONE 2026-07-18: C20 100 nF
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(C1525) + C21 1 µF 0603 (C15849) on ETH_3V3, placed against
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J2's pin column — as close to pins 4/5 as the In1 plane void
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allows while keeping short GND vias.
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- [x] D4/D5 (USBLC6 on the PHY pairs) — RESOLVED 2026-07-17: **keep,
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exactly as drawn.** ST explicitly rates USBLC6 for Ethernet;
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PHY-side placement guards residual coupling through the
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@@ -63,14 +64,11 @@ W5100S reference schematic, and JLCPCB manufacturing limits. ERC/DRC: clean.
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stub (stub inductance adds L·di/dt let-through). Layout: route
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the pair in-line through the package, near J2, short GND via on
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pin 2. If ever bypassing at bring-up: desolder + jumper 1–6/3–4.
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- [ ] **FT2232H EEPROM interface** (`Usb Connector.kicad_sch`) — schematic
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part DONE 2026-07-17 per datasheet Table 3.4: U7.4 (DO) moved to new
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net EE_DO; R30 (2.2 kΩ, C25879) inserted EE_DO→EE_DATA; R31 (10 kΩ,
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C25744) pull-up EE_DO→3V3. EEDATA→DI stays direct. ERC 0, netlist
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verified, BOM fields populated. Remaining (PCB rework):
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- [ ] Place/route R30 + R31 near U7 (Update PCB from Schematic pulls
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them in together with the 6 MDI termination parts — 8 new
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footprints total).
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- [x] **FT2232H EEPROM interface — DONE (schematic + PCB)** per datasheet
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Table 3.4: U7.4 (DO) moved to new net EE_DO; R30 (2.2 kΩ, C25879)
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inserted EE_DO→EE_DATA; R31 (10 kΩ, C25744) pull-up EE_DO→3V3.
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EEDATA→DI stays direct. R30/R31 placed 4–5 mm from U7, routed, DRC
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parity 0. ERC 0, netlist verified, BOM fields populated.
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## Functional / robustness
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@@ -131,8 +129,8 @@ W5100S reference schematic, and JLCPCB manufacturing limits. ERC/DRC: clean.
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iceprog-pin-mapping decision above (changes the schematic).
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- [ ] CC1/CC2 have no ESD protection (USBLC6 covers D+/D− only) — optional,
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most hobby designs skip; note spare-channel budget if respinning D2 area.
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- [ ] Ensure `hardware/re-bba-rb/.history/` (contains an embedded `.git`) is
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gitignored and never committed.
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- [x] `.history/` (embedded `.git`) — VERIFIED ignored via root
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`.gitignore:28`, nothing tracked.
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## Minor / BOM
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@@ -142,10 +140,10 @@ W5100S reference schematic, and JLCPCB manufacturing limits. ERC/DRC: clean.
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(Y1 YXC X322512MOB4SI / C70565, Y2 X322525MOB4SI / C9006, both JLC
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Basic, ±10 ppm) — correct for the 18 pF load caps and the W5100S
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Table 9 recommendation. No change needed.
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- [ ] 12 V-rail parts ≥ 25 V rating: C3, C4 (10 µF 0805), C6, C65 (100 µF
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electrolytic); D3 SMAJ12A already correct.
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- [ ] 1 % tolerance required: R1/R2 (buck VFB divider, TI requirement),
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R10 (FTDI REF 12 k), R16 (RSET_BG), R3/R4 (PR1 divider).
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- [x] 12 V-rail parts ≥ 25 V — VERIFIED in BOM audit 2026-07-17: C3/C4 25 V,
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C6 50 V, C65 25 V (Lelon SMD electrolytic); D3 SMAJ12A correct.
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- [x] 1 % tolerance — VERIFIED in BOM audit 2026-07-17: R1/R2, R3/R4, R10,
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R16 are all 1 % UNI-ROYAL parts (and new R26–R35 are 1 %).
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- [ ] TPS22810 CT: floating = fastest ramp (~0.7 A inrush into ETH rail
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caps). Consider CT = 10 nF footprint (DNP-able).
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- [ ] Verify HR911105A internal LED pinout (assumed: 9/12 anodes via
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@@ -173,7 +171,10 @@ W5100S reference schematic, and JLCPCB manufacturing limits. ERC/DRC: clean.
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pin-compatible, but treat as a bring-up suspect if EXI ESD behaviour
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looks odd. C65 is an SMD electrolytic (Lelon VZH101M1ETR-0607, 25 V) —
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assembly-friendly, not THT as first assumed.
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- [ ] Check fiducials for SMT assembly.
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- [ ] Fiducials: VERIFIED ABSENT (0 on the board, 2026-07-18). JLCPCB can
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panel-add their own, but 3 board fiducials (1 mm copper dot, 2 mm mask
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opening, asymmetric corners) is the robust choice — add with the debug
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LEDs/test points pass.
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## Housekeeping (repo) — done 2026-07-17
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