Close out functional/robustness findings: iceprog rewire, PR1, ETH_RST, debug provisions

Schematic fixes (PCB placement/routing of new parts pending, F8 lists them): - FTDI rewired to stock iceprog convention: FLASH_CS ADBUS3->ADBUS4, CDONE ACBUS1->ADBUS6, CRESET ACBUS0->ADBUS7 (old pins NC). With a blank 93LC46B (default 0403:6010) stock iceprog now works unmodified; EEPROM workflow decided: ship blank, FT_PROG optional (keep VID/PID). - TPS2116 PR1 divider: R3 200k->150k (C25755) - switchover now at 2.30-2.70V worst case instead of 20mV under the 3.3V rail. - ETH_RST: R36 10k pull-up to ETH_3V3 (RSTn floats during FPGA config). - Debug provisions: D6 green heartbeat LED (C72043) on FPGA pin 47, D7 red EXI-activity LED (C2286) on pin 48, 330R C25104 series; J4 6-pin LA header (GND + DBG0-4 = pins 9/10/11/12/6, unpopulated); TP1-TP5 test points (3V3/1V2/ETH_3V3/GC_ON/GND, in_bom no); FID1-3 fiducials placed board-only on the PCB, track-clearance checked. - Embedded Device:LED / Connector:TestPoint / Conn_01x06 lib symbols. Closed by analysis (no change): TPS22810 CT cap unnecessary (DS Table 2: ~98us rise at 3.3V with CT=0 -> ~0.5A inrush); RSET_BG 12.4k accepted (12.3k is E192; WIZnet ref synthesizes it as 12k+300R; 0.8% immaterial). Verified: ERC 0; netlist 132 vs BOM 125 differing only by the 7 deliberate in_bom=no items (J3, J4, TP1-5); LED polarity and TP rails confirmed in netlist; PCB DRC 0 errors with fiducials placed. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
2026-07-18 21:03:45 +00:00
parent bad2b54574
commit d0426b38fe
6 changed files with 2729 additions and 80 deletions
@@ -43375,4 +43375,118 @@
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