Close out functional/robustness findings: iceprog rewire, PR1, ETH_RST, debug provisions

Schematic fixes (PCB placement/routing of new parts pending, F8 lists them):
- FTDI rewired to stock iceprog convention: FLASH_CS ADBUS3->ADBUS4,
  CDONE ACBUS1->ADBUS6, CRESET ACBUS0->ADBUS7 (old pins NC). With a
  blank 93LC46B (default 0403:6010) stock iceprog now works unmodified;
  EEPROM workflow decided: ship blank, FT_PROG optional (keep VID/PID).
- TPS2116 PR1 divider: R3 200k->150k (C25755) - switchover now at
  2.30-2.70V worst case instead of 20mV under the 3.3V rail.
- ETH_RST: R36 10k pull-up to ETH_3V3 (RSTn floats during FPGA config).
- Debug provisions: D6 green heartbeat LED (C72043) on FPGA pin 47,
  D7 red EXI-activity LED (C2286) on pin 48, 330R C25104 series; J4
  6-pin LA header (GND + DBG0-4 = pins 9/10/11/12/6, unpopulated);
  TP1-TP5 test points (3V3/1V2/ETH_3V3/GC_ON/GND, in_bom no); FID1-3
  fiducials placed board-only on the PCB, track-clearance checked.
- Embedded Device:LED / Connector:TestPoint / Conn_01x06 lib symbols.

Closed by analysis (no change): TPS22810 CT cap unnecessary (DS Table 2:
~98us rise at 3.3V with CT=0 -> ~0.5A inrush); RSET_BG 12.4k accepted
(12.3k is E192; WIZnet ref synthesizes it as 12k+300R; 0.8% immaterial).

Verified: ERC 0; netlist 132 vs BOM 125 differing only by the 7
deliberate in_bom=no items (J3, J4, TP1-5); LED polarity and TP rails
confirmed in netlist; PCB DRC 0 errors with fiducials placed.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

hardware/re-bba-rb/Power.kicad_sch

@@ -2588,7 +2588,7 @@
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+		(property "Value" "150k"
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@@ -2632,7 +2632,7 @@
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-		(property "MPN" "0402WGF2003TCE"
+		(property "MPN" "0402WGF1503TCE"
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@@ -2654,7 +2654,7 @@
 				)
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-		(property "LCSC" "C25764"
+		(property "LCSC" "C25755"
 			(at 0 0 0)
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hardware/re-bba-rb/TODO.md

@@ -72,15 +72,19 @@ remaining work is the Functional/Broader/ordering lists below.
 
 ## Functional / robustness
 
-- [ ] **iceprog pin mismatch**: iceprog hardcodes CS=ADBUS4, CDONE=ADBUS6,
+- [ ] **iceprog pin mismatch — schematic FIXED 2026-07-18**: FLASH_CS moved
-      CRESET=ADBUS7. Board uses FLASH_CS=ADBUS3, CDONE=ACBUS1, CRESET=ACBUS0.
+      ADBUS3→ADBUS4 (U8 pin 21), CDONE ACBUS1→ADBUS6 (pin 23), CRESET
-      Rewire to the iCEbreaker convention, or maintain a patched iceprog.
+      ACBUS0→ADBUS7 (pin 24) — now exactly stock iceprog / iCEbreaker
-- [ ] **TPS2116 PR1 divider margin**: 200k/100k gives PR1 = 1.10 V vs
+      channel-A convention; old pins are NC. Pull-ups R11/R12 unchanged.
-      VREF = 1.0 V ±8 % (max 1.08 V) — 20 mV worst-case margin against the
+      - [ ] PCB: reroute the three lines to the new U8 pins (F8 shows the
-      3.3 V buck output. Change R3 to 150 k → switchover at 2.30–2.70 V.
+            pad-net changes).
-- [ ] **ETH_RST pull-up**: W5100S RSTn is a plain input (no internal pull) and
+- [x] **TPS2116 PR1 divider margin — FIXED 2026-07-18**: R3 200k→150k
-      floats while the FPGA configures. Add 10 k to **ETH_3V3** (not 3V3, so
+      (0402WGF1503TCE, LCSC C25755). PR1 = 1.32 V nominal; switchover at
-      it sits low when the ETH rail is off).
+      GC_3V3 = 2.30–2.70 V worst-case — safely below the 3.3 V rail. (Value
+      change only, same footprint — no PCB work.)
+- [ ] **ETH_RST pull-up — schematic FIXED 2026-07-18**: R36 10 k (C25744)
+      from ETH_RST to **ETH_3V3** (low when ETH rail off).
+      - [ ] PCB: place/route R36 near U11 pin 48.
 - [ ] **Gateware: gate all outputs on GC_ON** — when GC_ON=0 the W5100S is
       unpowered (U12) and the GC is off, but FPGA banks stay at 3.3 V. Hold
       the W5100S bus and EXI outputs Hi-Z/low to avoid back-powering.
@@ -93,23 +97,37 @@ remaining work is the Functional/Broader/ordering lists below.
 ## Broader items (beyond the wiring review — block fab on the first two)
 
 - [ ] **Write the re-bba-rb pin constraints** — `exi_bba/synth.py` still targets
-      the iCEbreaker. This board: EXI on FPGA pins 3 (IOB_9b), 4 (IOB_8a),
+      the iCEbreaker. Full board pin map: EXI_MOSI = 4 (IOB_8a, in),
-      44 (EXI_CLK, G6), 45 (EXI_CS), 46 (EXI_INT); W5100S bus on the IOT bank
+      EXI_MISO = 3 (IOB_9b, out), EXI_CLK = 44 (G6), EXI_CS = 45,
-      (23–43); CLK12 on 20 (G3); GC_ON on 21; ETH_RST on 2; UART on 18/19.
+      EXI_INT = 46; W5100S bus on the IOT bank (23–43); CLK12 = 20 (G3);
-      This is where the DO/DI swap and the UART crossover (UART_TXD = FTDI
+      GC_ON = 21; ETH_RST = 2; UART: FPGA RX = 18 (net UART_TXD!, FTDI
-      output = FPGA RX) get resolved. Pure software; do it before ordering to
+      output), FPGA TX = 19; **debug: LED_G = 47 (heartbeat), LED_R = 48
-      prove the pinout.
+      (EXI activity), DBG0–4 = 9/10/11/12/6 (J4 header)**. Pure software;
-- [ ] **Add debug provisions — the board currently has none.** RGB0–2 are
+      do before ordering to prove the pinout.
-      unconnected, no LEDs, no button, no test points; the CLAUDE.md bring-up
+- [ ] **Debug provisions — schematic DONE 2026-07-18** (was: board had none):
-      plan (StatusPanel heartbeat/activity LEDs + BTN re-init) has nothing to
+      - D6 green heartbeat LED (Everlight 19-217/GHC-YR1S2/3T, C72043,
-      drive. Spare IOBs: 6, 9, 10, 11, 12, 13, 47, 48. Add ≥2 LEDs (heartbeat,
+        Basic) on FPGA pin 47 (LED_G) via R37 330 Ω (C25104);
-      EXI activity), a 4–6 pin debug header (logic-analyzer access — EXI
+      - D7 red EXI-activity LED (KENTO KT-0603R, C2286, Basic) on pin 48
-      CLK/CS/MOSI/MISO are what you probe when enumeration fails), and test
+        (LED_R) via R38;
-      points on 3V3 / 1V2 / ETH_3V3 / GC_ON. Cannot be retrofitted.
+      - J4 6-pin debug header (unpopulated, in_bom no): GND + DBG0–4 =
-- [ ] **Verify mechanical fit** — outline + finger geometry vs SP1ETH/ETH2SP1
+        FPGA pins 9/10/11/12/6 — route EXI CLK/CS/MOSI/MISO copies here in
-      references (per CLAUDE.md), RJ45 and USB-C protrusion vs the GC serial
+        gateware for logic-analyzer bring-up;
-      port bay opening. An earlier commit says "need to remeasure PCB outline";
+      - TP1 3V3, TP2 1V2, TP3 ETH_3V3 (ethernet sheet), TP4 GC_ON, TP5 GND
-      sp1_test_plug validates pads only, not the envelope.
+        (1.5 mm pads, in_bom no);
+      - FID1–3 fiducials placed directly on the PCB (board-only) at
+        (195, 68.5)/(131, 48)/(163, 44.5) — copper-clear, DRC 0.
+      - [ ] PCB: place/route the 11 schematic footprints (D6/D7, R36/R37/
+            R38, TP1–5, J4) — F8 pulls them in. LEDs need visibility with
+            the GC shell on: place near the RJ45/USB edge if possible.
+- [ ] **Verify mechanical fit** (bench item — cannot be verified in repo):
+      outline vs the SP1 slot, RJ45/USB-C protrusion vs the GC serial port
+      bay opening. An earlier commit says "need to remeasure PCB outline".
+      Note 2026-07-18: the J3 footprint (12 contacts, 1 mm effective pitch,
+      two staggered depth rows, front-side only, fingers to the board edge
+      per the .kicad_dru exception) is the geometry derived from the
+      physical sp1_test_plug iterations — the test-plug project itself
+      contains no reusable finger footprint to diff against, so the
+      provenance is the physical test, not a file comparison.
 - [x] **SP1 12 V rail viability — VERIFIED against existing projects
       (2026-07-17).** webhdx's IDE-EXI v2 for Serial Port 1 (which became the
       commercial M.2 Loader): "New switching power regulator supplies 3.3V@2A
@@ -123,10 +141,12 @@ remaining work is the Functional/Broader/ordering lists below.
       12 V unused (runs from the 3.3 V pins). Remaining bench check only:
       - [ ] inrush into C65 (100 µF) + 2×10 µF buck input caps at GC power-on
             (the M.2 Loader precedent suggests this is a non-issue).
-- [ ] **Decide FT2232H EEPROM contents + flashing workflow** — blank 93LC46B
+- [x] **FT2232H EEPROM contents + flashing workflow — DECIDED 2026-07-18**:
-      enumerates with default VID/PID (works, generic); custom
+      ship with a **blank** 93LC46B. FT2232H falls back to its default
-      VID/PID/serial/product string needs FT_PROG provisioning. Tied to the
+      config (VID 0403 / PID 6010, dual channel, MPSSE on channel A) —
-      iceprog-pin-mapping decision above (changes the schematic).
+      exactly what stock iceprog opens by default, which now matches the
+      rewired pins. Optionally program serial/product string later with
+      FT_PROG (do NOT change VID/PID, or iceprog needs -d vid:pid).
 - [ ] CC1/CC2 have no ESD protection (USBLC6 covers D+/D− only) — optional,
       most hobby designs skip; note spare-channel budget if respinning D2 area.
 - [x] `.history/` (embedded `.git`) — VERIFIED ignored via root
@@ -134,8 +154,11 @@ remaining work is the Functional/Broader/ordering lists below.
 
 ## Minor / BOM
 
-- [ ] RSET_BG: datasheet says 12.3 kΩ 1 % (ref schematic: 12 k + 300 Ω);
+- [x] RSET_BG 12.4 k — ACCEPTED 2026-07-18 (closed, no change): datasheet
-      board has 12.4 k (~0.8 % off). Match if convenient.
+      says 12.3 kΩ, but that is an E192 value with no JLC Basic part —
+      WIZnet's own reference synthesizes it as 12 k + 300 Ω. The 0.8 %
+      deviation on a bandgap bias resistor is immaterial (well under the
+      combined tolerance of the ref design's two 1 % parts).
 - [x] Crystals Y1/Y2 — VERIFIED 2026-07-17: the BOM parts are both CL = 12 pF
       (Y1 YXC X322512MOB4SI / C70565, Y2 X322525MOB4SI / C9006, both JLC
       Basic, ±10 ppm) — correct for the 18 pF load caps and the W5100S
@@ -144,8 +167,11 @@ remaining work is the Functional/Broader/ordering lists below.
       C6 50 V, C65 25 V (Lelon SMD electrolytic); D3 SMAJ12A correct.
 - [x] 1 % tolerance — VERIFIED in BOM audit 2026-07-17: R1/R2, R3/R4, R10,
       R16 are all 1 % UNI-ROYAL parts (and new R26–R35 are 1 %).
-- [ ] TPS22810 CT: floating = fastest ramp (~0.7 A inrush into ETH rail
+- [x] TPS22810 CT — NOT NEEDED 2026-07-18 (closed, no change): datasheet
-      caps). Consider CT = 10 nF footprint (DNP-able).
+      Table 2 shows the internal ramp dominates at low VIN — rise time at
+      VIN = 3.3 V is ~98 µs even with CT = 0 (vs 102 µs at CT = 1 nF).
+      Inrush ≈ 15 µF × 3.3 V / 98 µs ≈ 0.5 A for <100 µs — trivial for the
+      2 A buck. A CT cap would buy nothing measurable.
 - [ ] Verify HR911105A internal LED pinout (assumed: 9/12 anodes via
       R14/R15 330 Ω to ETH_3V3, 10/11 cathodes to LNKn/ACTn) and the
       Bob-Smith common on pin 8 (tied straight to GND here; WIZnet ref

hardware/re-bba-rb/Usb Connector.kicad_sch

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@@ -5879,7 +5867,7 @@
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@@ -5978,7 +5966,7 @@
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@@ -13488,4 +13476,16 @@
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+	(no_connect
+		(at 276.86 107.95)
+		(uuid "dbe89d3c-f430-43e2-93d4-43b2adfa735f")
+	)
 )

hardware/re-bba-rb/ethernet.kicad_sch

@@ -6517,6 +6517,130 @@
 			)
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+	
+(symbol "Connector:TestPoint"
+		(pin_numbers
+			(hide yes)
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@@ -15981,4 +16105,278 @@
 			)
 		)
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+	(text "W5100S RSTn pull-up: RSTn is a plain\ninput (no internal pull) and floats while\nthe FPGA configures. Pulled to ETH_3V3\n(not 3V3) so it is low when ETH rail off."
+		(exclude_from_sim no)
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+		(instances
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+	(wire
+		(pts
+			(xy 259.08 110.49) (xy 259.08 113.03)
+		)
+		(stroke
+			(width 0)
+			(type default)
+		)
+		(uuid "b2a1faaa-31f8-4abd-bf6f-f483b2639004")
+	)
+	(label "ETH_RST"
+		(at 259.08 113.03 270)
+		(effects
+			(font
+				(size 1.27 1.27)
+			)
+			(justify left bottom)
+		)
+		(uuid "e22758d1-05a2-4d3b-bf3b-4ddf6cc78c26")
+	)
+	(symbol
+		(lib_id "Connector:TestPoint")
+		(at 264.16 104.14 0)
+		(unit 1)
+		(body_style 1)
+		(exclude_from_sim no)
+		(in_bom no)
+		(on_board yes)
+		(in_pos_files yes)
+		(dnp no)
+		(uuid "1193d498-9654-409a-9ac0-66959074d36e")
+		(property "Reference" "TP3"
+			(at 266.192 102.235 0)
+			(show_name no)
+			(do_not_autoplace no)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left)
+			)
+		)
+		(property "Value" "ETH_3V3"
+			(at 266.192 104.775 0)
+			(show_name no)
+			(do_not_autoplace no)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left)
+			)
+		)
+		(property "Footprint" "TestPoint:TestPoint_Pad_D1.5mm"
+			(at 264.16 104.14 0)
+			(hide yes)
+			(show_name no)
+			(do_not_autoplace no)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Datasheet" ""
+			(at 264.16 104.14 0)
+			(hide yes)
+			(show_name no)
+			(do_not_autoplace no)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Description" "Test point"
+			(at 264.16 104.14 0)
+			(hide yes)
+			(show_name no)
+			(do_not_autoplace no)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(pin "1"
+			(uuid "36a33547-93a5-4f08-afe3-5b24cfdf40d0")
+		)
+		(instances
+			(project "re-bba-rb"
+				(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/c2ddb95f-8a63-4bb0-b3f2-a27a372fea3a"
+					(reference "TP3")
+					(unit 1)
+				)
+			)
+		)
+	)
+	(wire
+		(pts
+			(xy 264.16 104.14) (xy 264.16 106.68)
+		)
+		(stroke
+			(width 0)
+			(type default)
+		)
+		(uuid "2fb7a116-988f-45e1-99ca-636bfc8b3abe")
+	)
+	(label "ETH_3V3"
+		(at 264.16 106.68 270)
+		(effects
+			(font
+				(size 1.27 1.27)
+			)
+			(justify left bottom)
+		)
+		(uuid "e334588c-685d-4bba-8229-40f8d701126a")
+	)
 )

hardware/re-bba-rb/re-bba-rb.kicad_pcb

@@ -43375,4 +43375,118 @@
 		)
 	)
 	(embedded_fonts no)
+	(footprint "Fiducial:Fiducial_1mm_Mask2mm"
+		(layer "F.Cu")
+		(uuid "7c1049eb-eb37-46a7-acd4-b131d8a59f4d")
+		(at 195 68.5)
+		(descr "Fiducial")
+		(property "Reference" "FID1"
+			(at 0 -1.8 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "0b7641ff-08bd-4106-a78c-ac2e1c6779f4")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Value" "Fiducial"
+			(at 0 1.8 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "de5dab09-f557-4764-9f60-aaf0d3cb5257")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(attr exclude_from_pos_files exclude_from_bom board_only allow_missing_courtyard)
+		(pad "" smd circle
+			(at 0 0)
+			(size 1 1)
+			(layers "F.Cu" "F.Mask")
+			(solder_mask_margin 0.5)
+			(uuid "9448c160-181c-4f7f-8fe4-4a5f2e0aef78")
+		)
+	)
+	(footprint "Fiducial:Fiducial_1mm_Mask2mm"
+		(layer "F.Cu")
+		(uuid "920178ef-aed2-4f9d-b6d3-4151cd8f2c06")
+		(at 131 48)
+		(descr "Fiducial")
+		(property "Reference" "FID2"
+			(at 0 -1.8 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "39e3bf42-36e8-4113-b002-392726e2d21d")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Value" "Fiducial"
+			(at 0 1.8 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "f30e9958-70a3-46d5-8afd-4493237b2fb5")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(attr exclude_from_pos_files exclude_from_bom board_only allow_missing_courtyard)
+		(pad "" smd circle
+			(at 0 0)
+			(size 1 1)
+			(layers "F.Cu" "F.Mask")
+			(solder_mask_margin 0.5)
+			(uuid "f34fc5fb-f2fe-4329-b7f4-027c89212188")
+		)
+	)
+	(footprint "Fiducial:Fiducial_1mm_Mask2mm"
+		(layer "F.Cu")
+		(uuid "609a5bc3-a7a3-4a32-9fee-9fe3e3f46424")
+		(at 163 44.5)
+		(descr "Fiducial")
+		(property "Reference" "FID3"
+			(at 0 -1.8 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "e05e62f4-2754-4811-97be-fef0e7858564")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Value" "Fiducial"
+			(at 0 1.8 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "4ef13df2-339c-4b45-ae69-29aea31a0101")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(attr exclude_from_pos_files exclude_from_bom board_only allow_missing_courtyard)
+		(pad "" smd circle
+			(at 0 0)
+			(size 1 1)
+			(layers "F.Cu" "F.Mask")
+			(solder_mask_margin 0.5)
+			(uuid "3e8df58d-fa1f-4ee9-ad18-e07897c57f1a")
+		)
+	)
 )