Implements the values worked out in 6ce7657.
R45 100k -> 33k ILIM 0.52 A -> 1.52 A (clears the 621 mA inrush)
R46 620k -> 150k ladder R1: 12V_RAW -> EN/UVLO
R47 100k -> 10k ladder R2: EN/UVLO -> OVLO
R48 NEW 12k \ ladder R3 = 14.2k: OVLO -> GND
R49 NEW 2.2k /
U13 pin 2 (OVLO) taken off GND and onto the new EFUSE_OVLO net
Verified: netlist shows 12V_RAW(R46.1) / EFUSE_EN(R46.2,R47.1,U13.5) /
EFUSE_OVLO(R47.2,R48.1,U13.2) / EFUSE_R3MID(R48.2,R49.1) / GND(R49.2,R45.2,
U13.4); 150 -> 152 components with none dropped (the malformed-property trap
from the kicad-bom-edit skill); ERC 0 violations.
PCB placement and routing still to do.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
The BOM was already fully populated (112/113 parts with MPN+LCSC) - this
audits it against the hardware-review requirements and closes the gaps:
- J3 (SP1 edge connector) set to in_bom=no: it is PCB gold fingers, not
a purchasable part. Netlist-vs-BOM count check now differs by exactly
this one deliberate exclusion.
- Crystals verified CL=12pF (Y1 C70565, Y2 C9006, both JLC Basic) -
matches the 18pF load caps and W5100S Table 9. TODO item closed.
- 12V-rail caps verified >=25V (C3/C4 25V, C6 50V, C65 Lelon 25V SMD
electrolytic); divider/REF/RSET resistors verified 1%.
- Noted: D2 LCSC C49383400 is the ElecSuper PUSB3AB6Z(ES) clone of the
Nexperia part (same DFN-7 package, 0.15pF) - pin-compatible.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
SP1 DO/DI naming is console-perspective (verified against SD Gecko and
SD2SP2 wiring): pin 6 DO = GC data out = adapter MOSI input, pin 9 DI =
GC data in = adapter MISO output. The design doc's SP1 table had the
roles reversed and the schematic followed it, putting the FPGA's MISO
driver on the GC-driven DO line (bus contention).
Fix keeps all PCB routing identical:
- Swap net names EXI_MOSI(_RAW) <-> EXI_MISO(_RAW) across exi/Fpga/root
sheets and the PCB (also renames the D2 PUSB3AB6 channel assignments).
- Swap R21 (22R) <-> R25 (33R) identities between the two footprint
positions so 33R stays on the FPGA-driven MISO line, 22R on the MOSI
input.
- Correct the SP1 pin table + MISO-tristate note in
docs/gc_bba_fpga_design.md (root cause).
Resulting board pin map (for the future board PCF): EXI_MOSI = FPGA
pin 4 (IOB_8a, input), EXI_MISO = pin 3 (IOB_9b, output).
Verified: ERC 0, DRC 0 errors with schematic parity 0, netlist shows
J3.6(DO)->R21->pin 4 and J3.9(DI)->R25->pin 3.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Roflin
Dennis Brentjes