The TPS25961's exposed pad is GND and the datasheet requires it be connected
to the GND plane (Table 5-1; package note 3 adds a mechanical requirement).
REVIEW.md claimed this was honoured because the footprint is the _ThermalVias
variant -- but the variant alone connects nothing. hardware/TPS25961.kicad_sym
defined pins 1-6 only, with no pin for the exposed pad, so KiCad had nothing to
map onto footprint pad 7 and left it netless: an isolated copper island under
the chip with its thermal vias going nowhere.
Adds pin 7 (GND, power_in, hidden, stacked on pin 4) to the symbol library, the
cached symbol in exi.kicad_sch, and the U13 instance.
PCB updated and verified: U13 pad 7 carries GND on all four elements (both SMD
rects and both thermal vias), R48 placed, EFUSE_OVLO routed, R49 gone. DRC
reports 0 violations, 0 unconnected pads and 0 schematic parity issues -- the
0-unconnected result is what confirms pad 7 is tied into the GND network rather
than merely labelled. The 4 DRC errors previously dismissed as zone-fill
phantoms on this pad are gone, though zones were refilled in the same pass so
that is not proof of cause either way.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
13 resistors carried Tolerance=5% while their MPN is a UNI-ROYAL 0402WG*F*
part -- F is the EIA code for +/-1% (J is 5%), and LCSC confirms the 1% rating.
The parts are 1%; only the metadata was wrong.
Worth fixing rather than leaving: the same part number appearing with two
different tolerances splits into two BOM lines under any grouping that
includes the field, and it misleads anyone sizing a divider. R48 in the eFuse
ladder was one of these (fixed in a9052c6) and there it was load-bearing --
at a genuine 5% the OVLO worst case reaches 17.05 V, over U3's 17 V limit,
versus 14.42-15.83 V at the correct 1%.
Metadata only; no circuit or part number changes.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Redraws the eFuse area with proper wires instead of labels-on-pins, and
simplifies the divider that 228ff03 added.
The first draft split R3 into 12 k + 2.2 k to hit 14.2 k, purely to preserve
the original ~8.9 V UVLO. That bought a fourth resistor and a named junction
net (EFUSE_R3MID) that nothing else touched. The ~9 V UVLO turned out to be
an assumption carried over from the original design rather than a requirement:
U3's minimum input is 4.5 V, so relaxing it to 6.78 V costs nothing and is in
fact less likely to chatter if the GC rail sags.
R46 620 k -> 100 k (C25741) R1: 12V_RAW -> EN/UVLO
R47 100 k -> 12.4 k (C11692) R2: EN/UVLO -> OVLO
R48 NEW 10 k (C25744) R3: OVLO -> GND
R49 removed
R45 100 k -> 33 k (C25779) ILIM 0.52 A -> 1.52 A
OVLO is unchanged at 15.18 V typ (14.47-15.78 worst case) against U3's 17 V
limit, so the simplification costs nothing on the parameter that matters.
Verified: 12V_RAW(R46.2) / EFUSE_EN(R46.1,R47.1,U13.5) / EFUSE_OVLO(R47.2,
R48.1,U13.2) / GND(R48.2,R45.2,U13.4); 152 -> 151 components with only R49
removed; ERC 0 violations.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Implements the values worked out in 6ce7657.
R45 100k -> 33k ILIM 0.52 A -> 1.52 A (clears the 621 mA inrush)
R46 620k -> 150k ladder R1: 12V_RAW -> EN/UVLO
R47 100k -> 10k ladder R2: EN/UVLO -> OVLO
R48 NEW 12k \ ladder R3 = 14.2k: OVLO -> GND
R49 NEW 2.2k /
U13 pin 2 (OVLO) taken off GND and onto the new EFUSE_OVLO net
Verified: netlist shows 12V_RAW(R46.1) / EFUSE_EN(R46.2,R47.1,U13.5) /
EFUSE_OVLO(R47.2,R48.1,U13.2) / EFUSE_R3MID(R48.2,R49.1) / GND(R49.2,R45.2,
U13.4); 150 -> 152 components with none dropped (the malformed-property trap
from the kicad-bom-edit skill); ERC 0 violations.
PCB placement and routing still to do.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
The BOM was already fully populated (112/113 parts with MPN+LCSC) - this
audits it against the hardware-review requirements and closes the gaps:
- J3 (SP1 edge connector) set to in_bom=no: it is PCB gold fingers, not
a purchasable part. Netlist-vs-BOM count check now differs by exactly
this one deliberate exclusion.
- Crystals verified CL=12pF (Y1 C70565, Y2 C9006, both JLC Basic) -
matches the 18pF load caps and W5100S Table 9. TODO item closed.
- 12V-rail caps verified >=25V (C3/C4 25V, C6 50V, C65 Lelon 25V SMD
electrolytic); divider/REF/RSET resistors verified 1%.
- Noted: D2 LCSC C49383400 is the ElecSuper PUSB3AB6Z(ES) clone of the
Nexperia part (same DFN-7 package, 0.15pF) - pin-compatible.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
SP1 DO/DI naming is console-perspective (verified against SD Gecko and
SD2SP2 wiring): pin 6 DO = GC data out = adapter MOSI input, pin 9 DI =
GC data in = adapter MISO output. The design doc's SP1 table had the
roles reversed and the schematic followed it, putting the FPGA's MISO
driver on the GC-driven DO line (bus contention).
Fix keeps all PCB routing identical:
- Swap net names EXI_MOSI(_RAW) <-> EXI_MISO(_RAW) across exi/Fpga/root
sheets and the PCB (also renames the D2 PUSB3AB6 channel assignments).
- Swap R21 (22R) <-> R25 (33R) identities between the two footprint
positions so 33R stays on the FPGA-driven MISO line, 22R on the MOSI
input.
- Correct the SP1 pin table + MISO-tristate note in
docs/gc_bba_fpga_design.md (root cause).
Resulting board pin map (for the future board PCF): EXI_MOSI = FPGA
pin 4 (IOB_8a, input), EXI_MISO = pin 3 (IOB_9b, output).
Verified: ERC 0, DRC 0 errors with schematic parity 0, netlist shows
J3.6(DO)->R21->pin 4 and J3.9(DI)->R25->pin 3.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Roflin
Dennis Brentjes