Documents everything examined in the 2026-07-17/18 review - not just
findings but full coverage with verdicts, so future sessions know what
not to re-review: per-sheet verification against datasheets and the
WIZnet reference design, the settled look-wrong-but-correct list
(VPHY/VPLL on 3.3V, D4/D5 floating VBUS + flow-through, EN at 12V,
RSET 12.4k, no CT cap, DO/DI direction evidence), PCB/JLC/BOM audit
state, explicit not-reviewed list (bench/gateware items), and a binding
rule to keep the file updated in the same commit as any change to a
reviewed circuit. Referenced from CLAUDE.md alongside TODO.md.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Schematic fixes (PCB placement/routing of new parts pending, F8 lists them):
- FTDI rewired to stock iceprog convention: FLASH_CS ADBUS3->ADBUS4,
CDONE ACBUS1->ADBUS6, CRESET ACBUS0->ADBUS7 (old pins NC). With a
blank 93LC46B (default 0403:6010) stock iceprog now works unmodified;
EEPROM workflow decided: ship blank, FT_PROG optional (keep VID/PID).
- TPS2116 PR1 divider: R3 200k->150k (C25755) - switchover now at
2.30-2.70V worst case instead of 20mV under the 3.3V rail.
- ETH_RST: R36 10k pull-up to ETH_3V3 (RSTn floats during FPGA config).
- Debug provisions: D6 green heartbeat LED (C72043) on FPGA pin 47,
D7 red EXI-activity LED (C2286) on pin 48, 330R C25104 series; J4
6-pin LA header (GND + DBG0-4 = pins 9/10/11/12/6, unpopulated);
TP1-TP5 test points (3V3/1V2/ETH_3V3/GC_ON/GND, in_bom no); FID1-3
fiducials placed board-only on the PCB, track-clearance checked.
- Embedded Device:LED / Connector:TestPoint / Conn_01x06 lib symbols.
Closed by analysis (no change): TPS22810 CT cap unnecessary (DS Table 2:
~98us rise at 3.3V with CT=0 -> ~0.5A inrush); RSET_BG 12.4k accepted
(12.3k is E192; WIZnet ref synthesizes it as 12k+300R; 0.8% immaterial).
Verified: ERC 0; netlist 132 vs BOM 125 differing only by the 7
deliberate in_bom=no items (J3, J4, TP1-5); LED polarity and TP rails
confirmed in netlist; PCB DRC 0 errors with fiducials placed.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
The 93LC46B's DO and DI were both tied directly to EEDATA, causing
drive contention during EEPROM read turnaround. Per the FT2232H
datasheet ("Connect directly to Data-In of the EEPROM and to Data-Out
of the EEPROM via a 2.2K resistor. Also, pull Data-Out of the EEPROM
to VCC via a 10K resistor"):
- U7.4 (DO) moved onto new net EE_DO
- R30 2.2k (UNI-ROYAL 0402WGF2201TCE, LCSC C25879, Basic) between
EE_DO and EE_DATA
- R31 10k (0402WGF1002TCE, C25744) pull-up from EE_DO to 3V3
- EEDATA -> DI (U7.3) stays direct
Schematic only; R30/R31 still need placing near U7 in the PCB rework.
Verified: ERC 0, EE_DATA = {U8.61, U7.3, R30.2}, EE_DO = {U7.4, R30.1,
R31.2}, R31.1 on global /Power/3V3 (no orphan local net), netlist
115 vs BOM 114 differing only by the deliberate J3 exclusion.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Dennis Brentjes
Roflin