Documents everything examined in the 2026-07-17/18 review - not just
findings but full coverage with verdicts, so future sessions know what
not to re-review: per-sheet verification against datasheets and the
WIZnet reference design, the settled look-wrong-but-correct list
(VPHY/VPLL on 3.3V, D4/D5 floating VBUS + flow-through, EN at 12V,
RSET 12.4k, no CT cap, DO/DI direction evidence), PCB/JLC/BOM audit
state, explicit not-reviewed list (bench/gateware items), and a binding
rule to keep the file updated in the same commit as any change to a
reviewed circuit. Referenced from CLAUDE.md alongside TODO.md.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Schematic fixes (PCB placement/routing of new parts pending, F8 lists them):
- FTDI rewired to stock iceprog convention: FLASH_CS ADBUS3->ADBUS4,
CDONE ACBUS1->ADBUS6, CRESET ACBUS0->ADBUS7 (old pins NC). With a
blank 93LC46B (default 0403:6010) stock iceprog now works unmodified;
EEPROM workflow decided: ship blank, FT_PROG optional (keep VID/PID).
- TPS2116 PR1 divider: R3 200k->150k (C25755) - switchover now at
2.30-2.70V worst case instead of 20mV under the 3.3V rail.
- ETH_RST: R36 10k pull-up to ETH_3V3 (RSTn floats during FPGA config).
- Debug provisions: D6 green heartbeat LED (C72043) on FPGA pin 47,
D7 red EXI-activity LED (C2286) on pin 48, 330R C25104 series; J4
6-pin LA header (GND + DBG0-4 = pins 9/10/11/12/6, unpopulated);
TP1-TP5 test points (3V3/1V2/ETH_3V3/GC_ON/GND, in_bom no); FID1-3
fiducials placed board-only on the PCB, track-clearance checked.
- Embedded Device:LED / Connector:TestPoint / Conn_01x06 lib symbols.
Closed by analysis (no change): TPS22810 CT cap unnecessary (DS Table 2:
~98us rise at 3.3V with CT=0 -> ~0.5A inrush); RSET_BG 12.4k accepted
(12.3k is E192; WIZnet ref synthesizes it as 12k+300R; 0.8% immaterial).
Verified: ERC 0; netlist 132 vs BOM 125 differing only by the 7
deliberate in_bom=no items (J3, J4, TP1-5); LED polarity and TP rails
confirmed in netlist; PCB DRC 0 errors with fiducials placed.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Insertion by Dennis; reviewed:
- DRC 0 errors / 0 unconnected / 0 schematic parity
- R32-R35 sit in-line between the termination cluster and D4/D5, each
aligned to its own line row; MDI_* stubs only 1.45-1.48mm, no new
vias, all pair copper at the ETH_DP 0.2mm width
- Pair skew after insertion: TX 0.66mm, RX 1.81mm - both far inside
the 100BASE-TX budget
- C20/C21 placed against J2's pin column, about as close as the In1
plane void allows while keeping short GND vias
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Completes the WIZnet reference schematic for the MDI section:
- R32-R35 3.3R 1% (YAGEO RC0402FR-073R3L, LCSC C137986) in series in
each MDI line per WIZnet note 6 (EMI damping). Chain per line is now
U11 pin -> 49.9R termination tap -> 3.3R -> D4/D5 flow-through -> J2.
Chip-side nets keep PHY_*; the D4/D5-side segments are renamed MDI_*
and added to the ETH_DP netclass patterns so the impedance DRC rules
police both halves.
- C20 100nF (C1525) + C21 1uF (C15849) on ETH_3V3 per WIZnet note 7 -
to be placed AT J2 pins 4/5 tapping the In2 ETH_3V3 island.
(Also carries KiCad's resave/reposition of ethernet.kicad_sch from the
rework session - netlist-identical, verified.)
Verified: ERC 0, netlist 121 components vs BOM 120 (J3-only delta),
PHY_TX_P = {U11.3, R26.1, R32.1}, MDI_TX_P = {R32.2, D4.1}, and
likewise for all four lines. PCB: 6 footprints to place (cut the lines
between termination and D4/D5 for R32-R35; C20/C21 at the jack).
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Per the WIZnet W5100S reference schematic (note 4: "to avoid the 100M
overshoot, place the 49.9 resistors and 0.1uF capacitor near the MDI
pin"): R26/R27 (49.9R 1%) from TXOP/TXON to a common node bypassed by
C18 (100nF) to GND, and R28/R29 + C19 likewise for RXIP/RXIN. Attached
on the PHY-side nets (chip side of D4/D5). BOM fields populated
(UNI-ROYAL 0402WGF4999TCE / LCSC C25120, Samsung CL05B104KO5NNNC /
C1525). Optional 3.3R series dampers deliberately omitted.
Schematic only - the 6 footprints still need placing/routing next to
U11 pins 2/3/5/6 (Update PCB from Schematic). DRC parity reports
exactly those 6 missing footprints and nothing else.
Verified: ERC 0, netlist 107->113 components, termination nets match
the reference topology.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Dennis Brentjes
Roflin