Documents everything examined in the 2026-07-17/18 review - not just
findings but full coverage with verdicts, so future sessions know what
not to re-review: per-sheet verification against datasheets and the
WIZnet reference design, the settled look-wrong-but-correct list
(VPHY/VPLL on 3.3V, D4/D5 floating VBUS + flow-through, EN at 12V,
RSET 12.4k, no CT cap, DO/DI direction evidence), PCB/JLC/BOM audit
state, explicit not-reviewed list (bench/gateware items), and a binding
rule to keep the file updated in the same commit as any change to a
reviewed circuit. Referenced from CLAUDE.md alongside TODO.md.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Schematic fixes (PCB placement/routing of new parts pending, F8 lists them):
- FTDI rewired to stock iceprog convention: FLASH_CS ADBUS3->ADBUS4,
CDONE ACBUS1->ADBUS6, CRESET ACBUS0->ADBUS7 (old pins NC). With a
blank 93LC46B (default 0403:6010) stock iceprog now works unmodified;
EEPROM workflow decided: ship blank, FT_PROG optional (keep VID/PID).
- TPS2116 PR1 divider: R3 200k->150k (C25755) - switchover now at
2.30-2.70V worst case instead of 20mV under the 3.3V rail.
- ETH_RST: R36 10k pull-up to ETH_3V3 (RSTn floats during FPGA config).
- Debug provisions: D6 green heartbeat LED (C72043) on FPGA pin 47,
D7 red EXI-activity LED (C2286) on pin 48, 330R C25104 series; J4
6-pin LA header (GND + DBG0-4 = pins 9/10/11/12/6, unpopulated);
TP1-TP5 test points (3V3/1V2/ETH_3V3/GC_ON/GND, in_bom no); FID1-3
fiducials placed board-only on the PCB, track-clearance checked.
- Embedded Device:LED / Connector:TestPoint / Conn_01x06 lib symbols.
Closed by analysis (no change): TPS22810 CT cap unnecessary (DS Table 2:
~98us rise at 3.3V with CT=0 -> ~0.5A inrush); RSET_BG 12.4k accepted
(12.3k is E192; WIZnet ref synthesizes it as 12k+300R; 0.8% immaterial).
Verified: ERC 0; netlist 132 vs BOM 125 differing only by the 7
deliberate in_bom=no items (J3, J4, TP1-5); LED polarity and TP rails
confirmed in netlist; PCB DRC 0 errors with fiducials placed.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Insertion by Dennis; reviewed:
- DRC 0 errors / 0 unconnected / 0 schematic parity
- R32-R35 sit in-line between the termination cluster and D4/D5, each
aligned to its own line row; MDI_* stubs only 1.45-1.48mm, no new
vias, all pair copper at the ETH_DP 0.2mm width
- Pair skew after insertion: TX 0.66mm, RX 1.81mm - both far inside
the 100BASE-TX budget
- C20/C21 placed against J2's pin column, about as close as the In1
plane void allows while keeping short GND vias
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
SP1 DO/DI naming is console-perspective (verified against SD Gecko and
SD2SP2 wiring): pin 6 DO = GC data out = adapter MOSI input, pin 9 DI =
GC data in = adapter MISO output. The design doc's SP1 table had the
roles reversed and the schematic followed it, putting the FPGA's MISO
driver on the GC-driven DO line (bus contention).
Fix keeps all PCB routing identical:
- Swap net names EXI_MOSI(_RAW) <-> EXI_MISO(_RAW) across exi/Fpga/root
sheets and the PCB (also renames the D2 PUSB3AB6 channel assignments).
- Swap R21 (22R) <-> R25 (33R) identities between the two footprint
positions so 33R stays on the FPGA-driven MISO line, 22R on the MOSI
input.
- Correct the SP1 pin table + MISO-tristate note in
docs/gc_bba_fpga_design.md (root cause).
Resulting board pin map (for the future board PCF): EXI_MOSI = FPGA
pin 4 (IOB_8a, input), EXI_MISO = pin 3 (IOB_9b, output).
Verified: ERC 0, DRC 0 errors with schematic parity 0, netlist shows
J3.6(DO)->R21->pin 4 and J3.9(DI)->R25->pin 3.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Dennis Brentjes
Roflin