Roflin
a082e15c4f
First silicon proof of the EXI capture path. A Pi bit-banging EXI into J4 reads the device ID 04 02 02 00 21/21, NWAYS 0x17, HIPR 0x01, writes and reads back PAR0-3, writes IMR, and sees NCRA's reset bit self-clear. Fixes two host-side bugs found getting there: - exi_devid_rpi.py sampled MISO just after the rising edge, racing the slave's own update and landing one bit early (04 came back as 08). Sample in the CLK-low phase, as the simulation does. - pi-exi-wirecheck.py's bridge scan drove HIGH against pull-downs, but the FPGA's SB_IO pull-up out-pulls the Pi's internal pull-down, so every pin reported as bridged. The aggressor now drives LOW against pull-ups. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
72 lines
3.2 KiB
Python
72 lines
3.2 KiB
Python
#!/usr/bin/env python3
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"""EXI device-ID query for re-bba-rb bring-up — run on a Raspberry Pi wired to
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the FPGA's EXI pins, to validate the GameCube-facing capture path with NO W5100
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involved (so it works even on a unit whose W5100/ethernet side is dead).
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It bit-bangs the EXI SPI the way the GameCube does: CLK idles HIGH; the FPGA
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samples MOSI on the falling edge and drives MISO on the rising edge. It sends
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the device-ID read header (read 4 bytes @ addr 0 = 0x00 0x03), then pauses (the
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GC pauses the clock between the header and the data so the FPGA can prefetch the
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response), then clocks read bytes and looks for the reply 04 02 02 00.
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Wiring (Pi BCM GPIO -> FPGA EXI, all 3.3 V, shared GND):
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CLK -> EXI CLK (FPGA pin 44)
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MOSI -> EXI MOSI (FPGA pin 4, an FPGA *input*)
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MISO <- EXI MISO (FPGA pin 3, an FPGA *output*)
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CS -> EXI CS (FPGA pin 45)
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GND <-> GND
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Reach these at the SP1 edge connector (J3) or on the series damper resistors.
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Edit the BCM pin numbers below to match your wiring. Run: sudo python3 exi_devid_rpi.py
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Requires the FPGA to be running the full BBA design (e.g. build/seed3/top.bin)
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and its 12 MHz clock (X1) alive — both independent of the W5100.
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"""
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import time
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try:
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import RPi.GPIO as GPIO
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except ImportError:
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raise SystemExit("needs RPi.GPIO -> sudo apt install python3-rpi.gpio")
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# ---- set these to your actual Pi BCM pin numbers ----
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CLK, MOSI, MISO, CS = 11, 10, 9, 8
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GPIO.setmode(GPIO.BCM)
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GPIO.setup(CLK, GPIO.OUT, initial=1) # CPOL=1: clock idles HIGH
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GPIO.setup(MOSI, GPIO.OUT, initial=0)
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GPIO.setup(CS, GPIO.OUT, initial=1) # inactive HIGH
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GPIO.setup(MISO, GPIO.IN)
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def xfer(b):
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"""Clock one byte MSB-first; FPGA samples MOSI on falling, drives MISO on rising."""
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r = 0
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for i in range(7, -1, -1):
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GPIO.output(MOSI, (b >> i) & 1) # MOSI stable while CLK is high
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GPIO.output(CLK, 0) # falling edge -> FPGA samples MOSI
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# Sample MISO HERE, while CLK is low. The FPGA drives MISO on the
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# RISING edge, so reading just after that edge races the slave's own
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# update and lands one bit position early (04 02 02 00 comes back as
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# 08 ...). The low phase is when the bit is settled.
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r = (r << 1) | GPIO.input(MISO)
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GPIO.output(CLK, 1) # rising edge -> FPGA drives next bit
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return r
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GPIO.output(CS, 0) # assert CS (active low)
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xfer(0x00) # header byte 0: read, addr[12:6]=0
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xfer(0x03) # header byte 1: addr[5:0]=0, len-1=3 (4 B)
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time.sleep(0.001) # gap so the FPGA can prefetch the reply
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resp = [xfer(0x00) for _ in range(6)] # clock a few read bytes
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GPIO.output(CS, 1) # deassert CS
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GPIO.cleanup()
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print("read bytes:", " ".join("%02x" % x for x in resp))
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want = [0x04, 0x02, 0x02, 0x00]
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found = any(resp[i:i + 4] == want for i in range(len(resp) - 3))
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if found:
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print("EXI device-ID 04 02 02 00 -> FOUND. EXI capture path works!")
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else:
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print("device-ID not found. Try: swap to mode-2 edges (move the MISO sample "
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"to just before the falling edge), check wiring/GND, confirm the FPGA "
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"is running the BBA design and its 12 MHz clock is alive.")
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