Dennis Brentjes
346 lines
17 KiB
Python
346 lines
17 KiB
Python
"""Synthesis script for BBATop → re-bba-rb interposer board (iCE40UP5K SG48).
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Run from workspace root:
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python -m exi_bba.synth # synthesize only
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python -m exi_bba.synth --flash # synthesize and flash
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This file re-declares IceBreakerPlatform inline so that importing
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rebbarb/rebbarb.py (which has a module-level platform.build() call) is avoided.
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"""
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import glob
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import os
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import re
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import subprocess
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import sys
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from amaranth import *
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from amaranth.build import *
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from amaranth.vendor import LatticeICE40Platform
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from exi_bba.bba_top import BBATop
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# ── Platform definition ───────────────────────────────────────────────────
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# Real re-bba-rb board pin map, pulled directly from the schematic netlist
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# (U9 = iCE40UP5K-SG48ITR) — not iCEbreaker PMOD placeholders.
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#
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# EXI (GC side) : CLK=44(G6) MOSI=4(IOB_8a) MISO=3(IOB_9b) CS=45 INT=46
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# W5100 bus (IOT bank, indirect parallel):
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# A0=42 A1=38 D0=34 D1=32 D2=31 D3=28 D4=27 D5=26 D6=25 D7=23
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# CS_N=43 RD_N=37 WR_N=36 RST_N=2 (net /ethernet/ETH_RST, NOT on the IOT
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# bank — separate pin)
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# Board ties the W5100's upper address lines A[14:2] to 0 (only A[1:0]
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# wired); DATA[7:0] is bidirectional (SB_IO tristate, shared output-enable).
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#
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# INT_N=13 — MOVED off the schematic's original pin 35: pin 35 physically
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# conflicts with the iCE40UP5K's PLL hard macro (nextpnr: "PLL bel
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# 'X12/Y31/pll_3' cannot be used... conflicts with input... on pin 35"),
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# and this design needs the PLL for the 54 MHz capture-domain clock. Pin 35
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# cannot be used as regular I/O at all while the PLL is instantiated,
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# regardless of what drives it — this is a fixed silicon constraint, not a
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# routing choice. Pin 13 was picked because it's the ONLY spare GPIO on this
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# exact SG48 package/board combo: the 5k-sg48 package has 39 usable I/O pins
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# total (per icestorm's icebox.py pin database), and every other one is
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# already assigned to a real signal on this board — pin 13 shows up in the
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# schematic netlist as an unrouted U9 pad, nothing else was available.
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# DONE on the board: the schematic + PCB now carry /ethernet/ETH_INT on U9
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# pin 13, and pin 35 is left unconnected (net
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# "unconnected-(U9A-IOT_46b_G0-Pad35)") so the PLL hard macro can claim it.
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# Verified against the schematic netlist 2026-07-31 — do not "restore" pin 35.
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#
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# Debug (J4 header, unpopulated): DBG0=9 DBG1=10 DBG2=11 DBG3=12 DBG4=6
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# UART (FT2232H channel B): net UART_TXD is the FTDI's OUTPUT, so it is the
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# FPGA's RX input, and vice versa for UART_RXD — FPGA RX=18(UART_TXD net),
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# FPGA TX=19(UART_RXD net). Do not swap by "TXD means transmit" instinct.
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# Status LEDs: D6(green,heartbeat)=LED_G=pin47, D7(red,EXI-activity)=LED_R=
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# pin48 — both wired ACTIVE-HIGH (LED anode toward the FPGA pin via its
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# series resistor, cathode to GND), unlike the iCEbreaker's own onboard
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# LEDs which are active-low. No physical button exists on this board (the
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# iCEbreaker's BTN_N was dev-board-only); panel_btn is tied idle instead.
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# RGB status LED (D11=red/rx, D12=green/tx, D13=yellow/ready) is on the
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# iCE40UP5K's dedicated SB_RGBA_DRV pins 39/40/41 — fixed by the chip
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# package on any board, not board-specific, so no resource needed here.
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class IceBreakerPlatform(LatticeICE40Platform):
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device = "iCE40UP5K"
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package = "SG48"
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default_clk = "clk12"
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resources = [
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Resource("clk12", 0,
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Pins("20", dir="i"),
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Clock(12e6),
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Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS")),
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# EXI interface (GC side, SPI Mode 3)
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Resource("exi", 0,
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Subsignal("clk", Pins("44", dir="i")),
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Subsignal("mosi", Pins("4", dir="i")),
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Subsignal("miso", Pins("3", dir="o")),
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Subsignal("cs_n", Pins("45", dir="i")),
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Subsignal("int_n", Pins("46", dir="o")),
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Attrs(IO_STANDARD="SB_LVCMOS")),
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# W5100 indirect parallel bus
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Resource("w5100", 0,
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Subsignal("addr", Pins("42 38", dir="o")),
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Subsignal("data", Pins("34 32 31 28 27 26 25 23", dir="io")),
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Subsignal("cs_n", Pins("43", dir="o")),
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Subsignal("rd_n", Pins("37", dir="o")),
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Subsignal("wr_n", Pins("36", dir="o")),
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Subsignal("int_n", Pins("13", dir="i")),
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Subsignal("rst_n", Pins("2", dir="o")),
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Attrs(IO_STANDARD="SB_LVCMOS")),
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# Bring-up status panel: D6/D7 discrete LEDs (active-high on this
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# board). RGB (pins 39/40/41) is driven via SB_RGBA_DRV — not
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# declared here as a platform resource (see BBATopSynth.elaborate).
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# No onboard button on this board (see note above).
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Resource("ledr", 0, Pins("48", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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Resource("ledg", 0, Pins("47", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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# UART debug console → FT2232H Channel B.
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# On the PC: open the second USB serial port at 115200 8N1.
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Resource("uart", 0,
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Subsignal("tx", Pins("19", dir="o")),
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Subsignal("rx", Pins("18", dir="i")),
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Attrs(IO_STANDARD="SB_LVCMOS")),
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]
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connectors = []
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def toolchain_program(self, products, name):
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iceprog = os.environ.get("ICEPROG", "iceprog")
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with products.extract(f"{name}.bin") as bitstream_filename:
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subprocess.check_call([iceprog, bitstream_filename])
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# ── BBATop with platform resource wiring ─────────────────────────────────
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class BBATopSynth(BBATop):
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"""BBATop with platform pin connections added in elaborate()."""
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def elaborate(self, platform):
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m = super().elaborate(platform)
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if platform is not None:
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exi = platform.request("exi", 0)
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w5100 = platform.request("w5100", 0)
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m.d.comb += [
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self.exi_clk .eq(exi.clk.i),
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self.exi_mosi .eq(exi.mosi.i),
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self.exi_cs_n .eq(exi.cs_n.i),
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exi.miso.o .eq(self.exi_miso),
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exi.int_n.o .eq(self.int_n),
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# W5100 parallel bus (DATA[7:0] bidirectional via SB_IO)
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w5100.addr.o .eq(self.w5100_addr),
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w5100.data.o .eq(self.w5100_data_o),
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w5100.data.oe .eq(self.w5100_data_oe),
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self.w5100_data_i.eq(w5100.data.i),
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w5100.cs_n.o .eq(self.w5100_cs_n),
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w5100.rd_n.o .eq(self.w5100_rd_n),
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w5100.wr_n.o .eq(self.w5100_wr_n),
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self.w5100_int_n .eq(w5100.int_n.i),
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w5100.rst_n.o .eq(self.w5100_rst_n),
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]
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# ── Bring-up status panel → onboard LEDs ────────────────────────
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# All 5 panel LEDs mapped:
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# LEDG (pin 47) = led[0] heartbeat
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# LEDR (pin 48) = led[1] EXI activity
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# RGB (pins 39/40/41) = led[2] rx / led[3] tx / led[4] ready
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# No physical button on this board — panel_btn tied idle/released.
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if self._status_panel:
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ledr = platform.request("ledr", 0)
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ledg = platform.request("ledg", 0)
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led = self.panel_led
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m.d.comb += [
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ledg.o.eq(led[0]), # heartbeat (active-high LED)
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ledr.o.eq(led[1]), # EXI activity (active-high LED)
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# all 3 bits idle/released (active-low idle = 1) — no
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# physical button exists on this board to read
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self.panel_btn.eq(C(0b111, 3)),
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]
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# iCEbreaker RGB LED has no series resistors — must use
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# SB_RGBA_DRV (raw pad driver with built-in current source).
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# RGB0=red→rx_act RGB1=green→tx_act RGB2=blue→ready
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# Verify colour-to-element mapping against schematic at bring-up.
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m.submodules.rgb_drv = Instance("SB_RGBA_DRV",
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p_CURRENT_MODE="0b1",
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p_RGB0_CURRENT="0b000001",
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p_RGB1_CURRENT="0b000001",
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p_RGB2_CURRENT="0b000001",
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i_CURREN=Const(1, 1),
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i_RGBLEDEN=Const(1, 1),
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i_RGB0PWM=led[2],
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i_RGB1PWM=led[3],
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i_RGB2PWM=led[4],
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o_RGB0=Signal(name="rgb_r"),
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o_RGB1=Signal(name="rgb_g"),
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o_RGB2=Signal(name="rgb_b"),
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)
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# ── UART debug console → FT2232H Channel B ─────────────────────
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if self._uart_console:
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uart = platform.request("uart", 0)
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m.d.comb += [
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uart.tx.o .eq(self.uart_tx),
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self.uart_rx .eq(uart.rx.i),
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]
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return m
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# ── Entry point ───────────────────────────────────────────────────────────
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#
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# Seed sweep: nextpnr placement is stochastic. With ~22% LC utilisation
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# routing dominates timing, so different seeds can vary fmax by ±20%.
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# Pass --seeds N to try N seeds (default 1, i.e. seed 1 only).
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# The build directory is reused across seeds; the final artefact in
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# build/top.bin is the result of the last (or best) seed tried.
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if __name__ == "__main__":
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do_flash = "--flash" in sys.argv
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n_seeds = next((int(sys.argv[i+1]) for i, a in enumerate(sys.argv)
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if a == "--seeds"), 1)
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print(f"Synthesizing BBATop for {IceBreakerPlatform.device}-"
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f"{IceBreakerPlatform.package} "
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f"(do_program={do_flash}, seeds=1..{n_seeds})")
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best_seed = 1
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best_fmax = 0.0
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results = [] # (seed, fmax_clk, fmax_capture, verdict), scored only
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for seed in range(1, n_seeds + 1):
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print(f"\n{'='*60}")
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print(f" Seed {seed}/{n_seeds}")
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print(f"{'='*60}")
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opts = (f"--opt-timing --seed {seed} --timing-allow-fail")
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# A Platform instance can only be built ONCE — amaranth's
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# TemplatedPlatform.prepare() does `assert not self._prepared`. Reusing
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# one platform across the sweep made seeds 2..N raise a bare
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# AssertionError (empty message, so the handler below printed nothing),
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# after which the fmax parser re-read the PREVIOUS seed's build/top.tim
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# and reported identical numbers for every seed — a sweep that looked
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# like it ran but never did. Build a fresh platform per seed.
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platform = IceBreakerPlatform()
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# Each seed gets its OWN build directory. Sharing one `build/top.tim`
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# across the sweep is not safe on this workspace: /workspace is a WSL2
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# drvfs (Windows drive) mount, and a re-read of a file just rewritten
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# by a child process can return stale or partially-flushed content.
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# That silently mis-scored the sweep — seeds were credited with other
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# seeds' numbers, including nextpnr's PRE-routing placement estimates
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# (which run ~8 MHz optimistic), so a 53.08 MHz FAIL got reported as a
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# 61.94 MHz PASS. Deleting the stale file first did NOT fix it; only
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# not sharing the path does. Do not "simplify" this back to build/.
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build_dir = f"build/seed{seed}"
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build_ok = True
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try:
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platform.build(BBATopSynth(status_panel=True, uart_console=True), do_program=False,
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verbose=True, nextpnr_opts=opts, build_dir=build_dir)
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except Exception as exc:
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# nextpnr exits non-zero even with --timing-allow-fail on some
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# versions; treat as non-fatal timing failure.
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build_ok = False
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print(f" [seed {seed}] build exception (timing?): "
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f"{type(exc).__name__}: {exc}")
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# Parse fmax from nextpnr log in build/top.tim (if present). Domain
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# names are 'clk' (exi/sync, 24 MHz target) and 'capture_clk'
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# (54 MHz target, the tighter constraint) — NOT 'exi', which never
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# matched any real log line (this regex silently reported 0.0 MHz
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# for every seed until fixed).
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# nextpnr reports each domain TWICE: once post-placement (an estimate)
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# and once post-routing. Only the post-route number is real, so take
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# the LAST occurrence of each domain — never the first.
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#
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# A seed is only scored if BOTH domains were actually found. Defaulting
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# a missing value to 0.0 and scoring it anyway is how this script once
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# declared "Best seed: 8 ... PASS" while seed 8 in fact failed at
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# 49.66 MHz: unparsed seeds silently mixed with real ones. An
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# unparseable seed must be reported and skipped, never ranked.
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fmax = {}
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for tf in sorted(set(glob.glob(f"{build_dir}/*.tim"))):
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try:
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# errors="replace": a decode hiccup must not abort the parse
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# and leave the seed looking like a legitimate 0.0 MHz result.
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with open(tf, errors="replace") as f:
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for line in f:
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m_ = re.search(
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r"Max frequency for clock\s+'(\w+)':\s*([\d.]+)\s*MHz", line)
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if m_:
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fmax[m_.group(1)] = float(m_.group(2))
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except OSError as exc:
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print(f" [seed {seed}] could not read {tf}: {exc}")
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if "clk" not in fmax or "capture_clk" not in fmax:
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print(f" [seed {seed}] NO USABLE TIMING REPORT "
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f"(found {sorted(fmax) or 'nothing'}) — NOT SCORED"
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f"{'' if build_ok else '; build also reported an error'}")
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continue
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fmax_clk, fmax_capture = fmax["clk"], fmax["capture_clk"]
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verdict = ("PASS" if fmax_capture >= 54.02 and fmax_clk >= 24.0
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else "FAIL")
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results.append((seed, fmax_clk, fmax_capture, verdict))
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print(f" [seed {seed}] clk fmax: {fmax_clk:.2f} MHz (target 24) "
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f"capture_clk fmax: {fmax_capture:.2f} MHz (target 54.02) "
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f"{verdict}"
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f"{'' if build_ok else ' [build reported an error]'}")
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# capture_clk is the binding constraint (tighter target, historically
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# the one that swings ±20% with seed) — rank seeds by it.
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if fmax_capture > best_fmax:
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best_fmax = fmax_capture
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best_seed = seed
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# Per-seed summary. capture_clk swings hard with seed on this design, so
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# the pass RATE matters as much as the best number — a design that only
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# closes on a minority of seeds has no real margin.
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print(f"\n{'='*60}")
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print(f" Seed sweep summary ({len(results)}/{n_seeds} seeds scored)")
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print(f"{'='*60}")
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print(f" {'seed':>4} {'clk (≥24)':>10} {'capture_clk (≥54.02)':>21} verdict")
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for seed, fc, fcap, verdict in results:
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print(f" {seed:>4} {fc:>10.2f} {fcap:>21.2f} {verdict}")
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n_pass = sum(1 for *_, v in results if v == "PASS")
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if results:
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print(f"\n passing seeds: {n_pass}/{len(results)} "
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f"({[s for s, *_, v in results if v == 'PASS']})")
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overall = "PASS" if best_fmax >= 54.02 else "FAIL"
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print(f"\nBest seed: {best_seed} capture_clk fmax: {best_fmax:.2f} MHz "
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f"(target 54.02) — {overall}")
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if overall == "PASS" and n_pass * 2 < len(results):
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print(" NOTE: a MINORITY of seeds close timing. The bitstream from "
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"the best seed is usable, but this design has little margin — "
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"treat any logic addition as likely to break timing.")
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# build/ now holds one subdirectory per seed; the flashable bitstream for
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# the best seed is build/seed<N>/top.bin. There is no top-level build/top.bin.
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if results:
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print(f"\nBitstream for best seed: build/seed{best_seed}/top.bin")
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if do_flash and overall == "FAIL":
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print("\nREFUSING TO FLASH: no seed met the capture-domain timing "
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"constraint. The EXI front-end samples a 27 MHz clock and will "
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"miss bits. Re-run with more seeds (--seeds 16) or reduce logic.")
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elif do_flash:
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print(f"\nFlashing with seed {best_seed}...")
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opts = f"--opt-timing --seed {best_seed} --timing-allow-fail"
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# Fresh platform again — the sweep above already consumed one per seed.
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# Reuse the best seed's own build dir so the flashed bitstream is the
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# one that was actually measured.
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IceBreakerPlatform().build(
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BBATopSynth(status_panel=True, uart_console=True), do_program=True,
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verbose=True, nextpnr_opts=opts, build_dir=f"build/seed{best_seed}")
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print("Done.")
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