Dennis Brentjes
206 lines
13 KiB
Markdown
206 lines
13 KiB
Markdown
# CPL rotation corrections — re-bba-rb
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`re-bba-rb-cpl.csv` is generated from `kicad-cli pcb export pos` (raw KiCad
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rotation values), **then hand-corrected** for the parts below before each
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regeneration. This file exists because that correction step is easy to lose
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silently — regenerating the CPL "the normal way" wipes it out, and there is
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no automated check that would catch that. Read this before touching the CPL.
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## Why this exists
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KiCad's per-footprint rotation is measured from an arbitrary reference baked
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into whoever drew that footprint — it does not reliably match what JLCPCB's
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placement machine expects. This is a well-known, generic problem (see
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`cpl_rotations_db.csv` from the JLCKicadTools / kicad-jlcpcb-tools projects
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for the community's attempt at a fix), but **the generic community
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correction table was tried on this board and found wrong** — it claims
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`LQFP-: 270°`, but on this exact board/toolchain pairing (KiCad 10 +
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`kicad-cli pcb export pos`, not the dedicated plugin) the raw LQFP/QFN
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rotation is already correct. The generic table's values are calibrated
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against that plugin's own raw-rotation baseline, which is not the same
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baseline `kicad-cli`'s raw CSV export produces (different Y-axis handling
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between the two tools). **Do not reapply the community table wholesale to
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this board.** Every correction below was derived per-part from direct visual
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verification against JLCPCB's placement-preview render, not from that table.
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## Rotation sign convention
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The CPL uses JLCPCB's Y-up coordinate frame (`kicad-cli`'s csv pos format
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already negates Y from KiCad's native Y-down). In that frame, **increasing
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rotation angle is counter-clockwise** (standard math convention). So when
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the user reports "needs N degrees clockwise", the correction applied is
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**`new = (old - N) % 360`**, not `+N`. Get this backwards and every fix
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lands 2×N off instead of correct.
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## How to reapply — copy this exact dict, don't reconstruct it from memory
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This is the complete, current correction set (all 16 parts). **Copy-paste
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this block, don't retype it from the table below or from memory** — the one
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time it was retyped from a section of prose instead of copied whole, U4 got
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silently dropped and shipped with a wrong rotation.
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```python
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import csv
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corrections = {
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'U7': 270, # SOIC-8, confirmed 2026-07-31 (net of +90 hypothesis + 180 more) — same net correction as U10
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'U10': 270, # SOIC-8, confirmed (net of +90 hypothesis + 180 more)
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'U11': -90, # LQFP-64, confirmed 2026-07-31 ("90 degrees clockwise") — SUPERSEDES the earlier "all large chips are right" report, see below
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'D1': -90, 'D4': -90, 'D5': -90, 'U12': -90, # SOT-23-6, reconstructed hypothesis
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'U1': -180, # SOT-23-5, confirmed (two -90 corrections)
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'U4': -90, # SOT-23-5, confirmed ("U4 is good")
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'Q1': 180, 'Q2': 180, # SOT-23 bottom layer, confirmed "upside down"
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'D2': -90, # custom footprint, confirmed "90 CW"
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'D3': 180, # SMA diode, confirmed "180"
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'C65': 180, # electrolytic cap, confirmed "180"
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'U2': -90, # SOT-583-8, confirmed "90 CW"
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'U3': 180, # custom SOT95P280X110-6N footprint, confirmed "180"
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} # positive = CCW, negative = CW
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with open('re-bba-rb-cpl.csv', newline='') as f:
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rows = list(csv.DictReader(f))
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for r in rows:
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if r['Designator'] in corrections:
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old = float(r['Rotation'])
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new = (old + corrections[r['Designator']]) % 360
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r['Rotation'] = f"{new:.6f}"
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with open('re-bba-rb-cpl.csv', 'w', newline='') as f:
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writer = csv.DictWriter(f, fieldnames=['Designator','Mid X','Mid Y','Layer','Rotation'])
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writer.writeheader()
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writer.writerows(rows)
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```
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If a new correction comes in from a placement-preview check, add it to
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*this* dict (and the table below), never work from a hand-copied subset.
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When regenerating the CPL from scratch (e.g. after a reroute or component
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move), **re-run `kicad-cli pcb export pos` for fresh positions, then
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reapply every correction below** — don't just diff/copy the old file, since
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positions can legitimately change while rotations still need the same
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correction offset applied on top.
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## Confirmed correct as-is — apply NO correction
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**These are the only parts that take zero correction.** Everything else in
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this section title's spirit but requiring a nonzero offset (like U4 below)
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lives in the corrections table, not here — filing U4 in this section
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previously (saying "confirmed good" without also flagging its required -90°
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delta) caused a real bug: a later reapplication pass built its correction
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dict from this section's prose and silently skipped U4, regenerating the
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CPL with U4 back at raw/wrong rotation. Don't repeat that — if a part needs
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*any* nonzero delta from raw, it belongs in the table below, full stop, even
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if that delta is "confirmed correct and needs no further correction beyond
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it."
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- **U8 (LQFP-48)**, **U9 (QFN-48)** — "all large chips are right" (user,
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direct placement-preview check). ⚠️ **That single report also covered U11,
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and U11 later turned out to need −90° after all** (direct check,
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2026-07-31). So the "large chips are fine" observation is now known to be
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wrong for at least one of the three parts it covered, and U8/U9 rest
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entirely on that same weakened report. Treat both as **unverified**, not
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settled — re-check them in the placement preview before assembly. Do not
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cite "all large chips are right" as evidence again.
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- **D8, D9 (LED_0603, bottom layer)** — verified 2026-07-31 by tracing the
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circuit rather than by eye, see "D8/D9 polarity" below. No correction.
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- **J2 (HR911105A magjack, rot=90° in the PCB file)** — not a CPL-rotation
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question (J2 doesn't need per-part correction below, it's not in the CPL
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correction set), but its physical orientation was independently verified:
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the RJ45 signal pins (pins 1–8, footprint local +Y) map to absolute −X
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under the board's 90° placement rotation, which correctly faces the
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board's tongue/cable-exit edge. Pin 1 appearing to "face outside the
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board" in the placement render is *expected*, not a defect — the RJ45
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contacts are always near the cable-insertion opening by construction.
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## Corrections applied (all currently in `re-bba-rb-cpl.csv`)
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Each row: designator, package, raw→corrected, confidence.
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| Ref | Package | Raw | Corrected | Confidence |
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|---|---|---|---|---|
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| U7 | SOIC-8 | 90° | **0°** (net: +90° reconstructed hypothesis, then +180° more, user-confirmed 2026-07-31) | **Confirmed.** Note this landed on exactly the same net correction as U10 (+270°), which retroactively makes the two SOIC-8 parts consistent — the original bare "+90°" hypothesis was wrong for *both*, in the same direction and by the same amount |
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| U11 | LQFP-64 | -90° | **180°** | **Confirmed** ("90 degrees clockwise", 2026-07-31). Previously filed as needing NO correction on the strength of "all large chips are right" — that report was wrong for this part. See the note in the no-correction section above: U8/U9 inherit the doubt |
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| U10 | SOIC-8 | 0° | **270°** (net: +90° reconstructed hypothesis, then +180° more, user-confirmed) | Partially confirmed — the +90° hypothesis alone was WRONG/incomplete (needed another 180° on top). **This means the SOIC "+90°" hypothesis should not be trusted for U7 either** without its own direct check, since it's now proven wrong at least once. |
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| U3 | custom `SOT95P280X110-6N` | 0° | **180°** | **Confirmed** ("180°") |
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| D1 | SOT-23-6 | 0° | **270°** | Reconstructed hypothesis — not independently re-confirmed |
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| D4 | SOT-23-6 | 180° | **90°** | Reconstructed hypothesis — not independently re-confirmed |
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| D5 | SOT-23-6 | 180° | **90°** | Reconstructed hypothesis — not independently re-confirmed |
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| U12 | SOT-23-6 | 180° | **90°** | Reconstructed hypothesis — not independently re-confirmed |
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| U1 | SOT-23-5 | 180° | **0°** (two corrections: -90° then another -90°, user-confirmed both times) | **Confirmed** by direct user feedback, twice |
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| U4 | SOT-23-5 | 0° | **270°** (-90°, the same family correction as D1/D4/D5/U12) | **Confirmed** — user checked and said "U4 is good" after this delta, no second correction needed (unlike U1) |
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| Q1 | SOT-23 (bottom layer) | -90° | **90°** | **Confirmed** ("upside down" = 180°, direction-agnostic) |
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| Q2 | SOT-23 (bottom layer) | -90° | **90°** | **Confirmed** (same as Q1) |
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| D2 | custom `SON50P110X213X50-7` | 0° | **270°** | **Confirmed** ("90° clockwise") |
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| D3 | `Diode_SMD:D_SMA` | 180° | **0°** | **Confirmed** ("180°", direction-agnostic) |
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| C65 | `Capacitor_SMD:CP_Elec_6.3x7.7` | 0° | **180°** | **Confirmed** ("180°", direction-agnostic) |
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| U2 | SOT-583-8 | 180° | **90°** | **Confirmed** ("90° clockwise") |
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**"Reconstructed hypothesis" parts (U7, U10, D1, D4, D5, U12) explained:**
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the user reported "SOIC and SOT chips are rotated 90°, direction unsure."
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Cross-referencing against *earlier* feedback in the same session — where a
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-90° correction had been applied to the top-layer SOT-23 parts and NOT
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flagged as wrong, while the same -90° applied to a SOIC part (U10) WAS
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flagged wrong — implies SOT-23 needs -90° and SOIC needs the opposite,
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+90°. This is indirect reasoning, not a fresh direct check, and **U1 later
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proved that even within one confirmed-wrong-by-90°-family, the correction
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does NOT reliably generalize per package type** (U1 and U4 are both
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SOT-23-5, both got the -90° family correction, but U1 needed a *second*
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-90° on top while U4 was already correct) — so treat every "reconstructed
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hypothesis" row above as **worth a fresh placement-preview check**, not
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settled fact, despite no contradicting feedback having come in since.
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## D8/D9 polarity — checked by circuit tracing, NOT by eye (2026-07-31)
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D8 was reported as *possibly* upside down because "it connects with its
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negative side to Q1". **That observation is correct behaviour, not a
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fault** — D8's cathode is *supposed* to face Q1. Tracing the net:
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```
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D8: 3V3 → R41 → D8.pad2 (A) ─ D8.pad1 (K) → Q1.pad3 (C) → Q1.pad2 (E) → GND
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Q1 is an NPN low-side switch, base Q1.pad1 ← R39.
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Current can only flow if the LED cathode is the Q1 end. ✔
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D9: 3V3 → Q2.pad2 (E) → Q2.pad3 (C) → R42 → D9.pad2 (A) ─ D9.pad1 (K) → GND
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Q2 is a PNP high-side switch, base Q2.pad1 ← R40.
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D9's cathode goes straight to GND; it does NOT touch Q2 directly. ✔
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```
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Both are `LED_SMD:LED_0603_1608Metric` on **B.Cu**, both at raw −90°, and
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both have pad 1 = cathode (the footprint's B.Fab chamfer marks the pad-1 /
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cathode end). Absolute pad geometry, with the back-layer X-mirror applied:
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| | pad 1 (K) | pad 2 (A) | anode's partner |
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|---|---|---|---|
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| D8 | (167.420, **47.300**) | (167.420, **48.875**) | R41 pad 2 at (166.170, 48.875) |
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| D9 | (164.940, **47.340**) | (164.940, **48.915**) | R42 pad 2 at (163.690, 48.917) |
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The anode pads land at the *same Y* as their series resistor's pad — that
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alignment is what confirms the back-layer mirror was applied correctly when
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computing these (get the mirror wrong and pad 1/2 swap, inverting the whole
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conclusion). Q1's collector pad sits at (165.350, 45.580), i.e. **above** D8
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in Y — the same side as D8's cathode. So "cathode faces Q1" is exactly right.
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**Both D8 and D9 are oriented identically** (cathode toward smaller Y). That
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is a useful invariant: they are the same part in the same circuit role, so if
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a future preview shows one of them needing a flip, *both* need it — a
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correction applied to only one of the pair is a mistake.
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Note this relationship is **mirror-invariant**: whether the assembler renders
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the bottom layer viewed-from-below or seen-through-the-board, "D8's cathode
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end is the end nearer Q1" stays true. So it is a safe thing to eyeball in a
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preview, unlike absolute left/right or up/down judgements on bottom-layer
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parts.
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## Parts never checked at all
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Every 0402/0603/0805 passive (R/C/L) except C65, J1/J3/J4 connectors, and
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anything else not listed in the corrections table above is sitting at
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**raw, unverified KiCad rotation** in the CPL. Passives in symmetric
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packages are usually fine raw (this matched observed behavior for the ones
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implicitly checked), but this has not been confirmed part-by-part the way
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the table above was.
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## Bottom line for whoever picks this up next
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Before ordering assembly, re-check the *entire* board in JLCPCB's (or
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whatever assembler's) placement preview — this file only covers what's been
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individually verified so far, not a general guarantee the CPL is correct.
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