rebbarb

T

Roflin ccc13d4302 docs: record EXI_J4 J4-header EXI merge + measured seed sweep

4/8 seeds pass capture, best seed 8 = 63.09 MHz (+17% margin) — same pass
rate as the default build, so the AND-merge costs no measurable timing.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>

2026-09-30 18:00:20 +00:00

.claude/skills

Correct EEPROM soft-brick record: partial write on undersized U7 kills enumeration

2026-08-22 18:57:52 +00:00

.devcontainer

Moved all components to F.Cu

2026-08-28 10:29:41 +02:00

diagrams

Adds diagrams.

2026-06-13 19:02:58 +02:00

docs

Fix EXI DO/DI swap: rename nets + swap damping resistors, no copper changes

2026-07-18 12:36:41 +00:00

examples

Added full design created with Claude

2026-06-13 18:35:38 +02:00

exi_bba

synth: optional EXI mirror on the J4 debug header (EXI_J4=1)

2026-09-30 17:54:24 +00:00

hardware

D9 USB LED: loose contact reflowed, now lights correctly

2026-09-30 17:38:17 +00:00

rebbarb

Added Debouncer ToggleButton and PulseButton

2025-09-20 22:44:04 +02:00

scripts

uart-console: document the venv interpreter needed under sudo

2026-09-30 17:39:32 +00:00

.dockerignore

Moved all components to F.Cu

2026-08-28 10:29:41 +02:00

.gitattributes

Adds a power_sch

2026-06-16 14:59:18 +02:00

.gitignore

Bring-up: W5100 bus self-test, eFuse OVLO bug, Pi SPI EXI host

2026-09-20 14:33:49 +00:00

capture.pcapng

Moved all components to F.Cu

2026-08-28 10:29:41 +02:00

CLAUDE.md

docs: record EXI_J4 J4-header EXI merge + measured seed sweep

2026-09-30 18:00:20 +00:00

requirements.txt

Added full design created with Claude

2026-06-13 18:35:38 +02:00

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