svgb/build/tb_top.Makefile

TB       = tb_top
SOURCES  = gb.sv cpu.sv ppu.sv idec.sv ctrl.sv alu.sv alu16.sv regbank.sv rom.sv ram.sv cart.sv tb_top.sv clkgen.sv
INCLUDES = cpu_pkg.svh sva_common.svh
PATH_SRC = ../rtl:../rtl/cpu:../rtl/ppu:../sim

DEFINES = SVA_ENABLE

include ../synthflow/vivado/Makefile.rules
Initial work on build system Simple makefile to build testbench in vivado. Testbench currently just has a clock and a reset. Empty gb top module. 2021-02-15 22:40:12 +01:00			`TB = tb_top`
Starting work on a simple cartridge In order to get through bootstrap process 2023-10-02 22:56:19 +02:00			`SOURCES = gb.sv cpu.sv ppu.sv idec.sv ctrl.sv alu.sv alu16.sv regbank.sv rom.sv ram.sv cart.sv tb_top.sv clkgen.sv`
Complete rewrite from scratch, bootstrap WIP Rewrite to use several bus multiplexers, resulting into a less messy microarchitecture (hopefully). Some more room for cleanup though... Supports every instruction from the bootstrap rom, more or less. LY hacked at 0x90 to progress through vsync instantly. No cartridge is present yet, so we will always fail checksum test and lock up. 2023-10-02 00:00:56 +02:00			`INCLUDES = cpu_pkg.svh sva_common.svh`
WIP PPU LX/LY registers Removed second reg16 read port - no longer needed. 2023-10-03 21:44:28 +02:00			`PATH_SRC = ../rtl:../rtl/cpu:../rtl/ppu:../sim`
Initial work on reading instructions from bootROM 2021-02-15 23:55:09 +01:00
Complete rewrite from scratch, bootstrap WIP Rewrite to use several bus multiplexers, resulting into a less messy microarchitecture (hopefully). Some more room for cleanup though... Supports every instruction from the bootstrap rom, more or less. LY hacked at 0x90 to progress through vsync instantly. No cartridge is present yet, so we will always fail checksum test and lock up. 2023-10-02 00:00:56 +02:00			`DEFINES = SVA_ENABLE`
Initial work on build system Simple makefile to build testbench in vivado. Testbench currently just has a clock and a reset. Empty gb top module. 2021-02-15 22:40:12 +01:00
Complete rewrite from scratch, bootstrap WIP Rewrite to use several bus multiplexers, resulting into a less messy microarchitecture (hopefully). Some more room for cleanup though... Supports every instruction from the bootstrap rom, more or less. LY hacked at 0x90 to progress through vsync instantly. No cartridge is present yet, so we will always fail checksum test and lock up. 2023-10-02 00:00:56 +02:00			`include ../synthflow/vivado/Makefile.rules`