WIP PPU LX/LY registers

Removed second reg16 read port - no longer needed.

rtl/cpu/regbank.sv

@@ -16,10 +16,8 @@ module regbank (
 
     input  reg8_t reg8_rselect_i,
     input  reg16_t reg16_rselect_i,
-    input  reg16_t reg16_rselect2_i,
     output logic [ 7:0] reg8_rdata_o,
     output logic [15:0] reg16_rdata_o,
-    output logic [15:0] reg16_rdata2_o,
 
     output logic [15:0] hl_o
 );
@@ -56,7 +54,6 @@ module regbank (
     assign reg8_rdata_o  = reg8_rselect_i[0] ? reg_r[reg8_rselect_i[2:1]][ 7:0] :
                                                reg_r[reg8_rselect_i[2:1]][15:8];
     assign reg16_rdata_o  = reg_r[reg16_rselect_i];
-    assign reg16_rdata2_o = reg_r[reg16_rselect2_i];
 
     assign hl_o = reg_r[REG16_HL];