Add chip selects to rom/ram
Slightly easier to work with ppu and cart memory spaces this way
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parent
fda176d3b5
commit
5f98c7346f
26
rtl/gb.sv
26
rtl/gb.sv
@ -26,11 +26,9 @@ logic rom_sel;
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logic [ 7:0] rom_rdata;
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logic [ 7:0] rom_rdata;
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logic hiram_sel;
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logic hiram_sel;
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logic hiram_we;
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logic [ 7:0] hiram_rdata;
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logic [ 7:0] hiram_rdata;
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logic vram_sel;
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logic vram_sel;
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logic vram_we;
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logic [ 7:0] vram_rdata;
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logic [ 7:0] vram_rdata;
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cpu cpu_inst (
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cpu cpu_inst (
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@ -50,8 +48,7 @@ ppu ppu_inst (
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.cpu_addr_i (cpu_addr),
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.cpu_addr_i (cpu_addr),
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.cpu_rdata_o(cpu_ppu_rdata),
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.cpu_rdata_o(cpu_ppu_rdata),
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.cpu_we_i (cpu_we),
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.cpu_we_i (cpu_we),
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.cpu_wdata_i(cpu_wdata),
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.cpu_wdata_i(cpu_wdata)
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.cpu_addr_sel_o(ppu_sel)
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);
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);
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assign rom_enable_r = '1;
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assign rom_enable_r = '1;
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@ -60,13 +57,10 @@ assign rom_sel = rom_enable_r & ~(|cpu_addr[15:8]);
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assign vram_sel = (cpu_addr[15:13] == 3'b100);
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assign vram_sel = (cpu_addr[15:13] == 3'b100);
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assign hiram_sel = (&cpu_addr[15:7]) & ~(&cpu_addr[6:0]);
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assign hiram_sel = (&cpu_addr[15:7]) & ~(&cpu_addr[6:0]);
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assign vram_we = vram_sel & cpu_we;
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assign cpu_rdata = rom_rdata |
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assign hiram_we = hiram_sel & cpu_we;
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vram_rdata |
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hiram_rdata |
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assign cpu_rdata = ({8{ rom_sel}} & rom_rdata) |
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cpu_ppu_rdata;
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({8{ vram_sel}} & vram_rdata) |
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({8{hiram_sel}} & hiram_rdata)|
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({8{ ppu_sel}} & cpu_ppu_rdata);
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rom #(
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rom #(
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.FILE_NAME("DMG_ROM.bin"),
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.FILE_NAME("DMG_ROM.bin"),
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@ -74,6 +68,8 @@ rom #(
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.DATA_W (8)
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.DATA_W (8)
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) rom_inst (
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) rom_inst (
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.clk (clk),
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.clk (clk),
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.nreset (nreset),
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.cs_i (rom_sel),
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.address_i(cpu_addr[7:0]),
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.address_i(cpu_addr[7:0]),
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.rdata_o (rom_rdata)
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.rdata_o (rom_rdata)
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);
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);
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@ -83,9 +79,11 @@ ram #(
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.DATA_W (8)
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.DATA_W (8)
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) vram_inst (
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) vram_inst (
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.clk (clk),
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.clk (clk),
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.nreset (nreset),
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.cs_i (vram_sel),
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.address_i (cpu_addr[12:0]),
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.address_i (cpu_addr[12:0]),
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.rdata_o (vram_rdata),
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.rdata_o (vram_rdata),
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.we_i (vram_we),
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.we_i (cpu_we),
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.wdata_i (cpu_wdata)
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.wdata_i (cpu_wdata)
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);
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);
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@ -94,9 +92,11 @@ ram #(
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.DATA_W (8)
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.DATA_W (8)
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) hiram_inst (
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) hiram_inst (
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.clk (clk),
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.clk (clk),
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.nreset (nreset),
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.cs_i (hiram_sel),
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.address_i (cpu_addr[6:0]),
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.address_i (cpu_addr[6:0]),
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.rdata_o (hiram_rdata),
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.rdata_o (hiram_rdata),
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.we_i (hiram_we),
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.we_i (cpu_we),
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.wdata_i (cpu_wdata)
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.wdata_i (cpu_wdata)
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);
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);
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13
rtl/ppu.sv
13
rtl/ppu.sv
@ -5,15 +5,12 @@ module ppu (
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input logic [15:0] cpu_addr_i,
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input logic [15:0] cpu_addr_i,
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output logic [ 7:0] cpu_rdata_o,
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output logic [ 7:0] cpu_rdata_o,
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input logic cpu_we_i,
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input logic cpu_we_i,
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input logic [ 7:0] cpu_wdata_i,
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input logic [ 7:0] cpu_wdata_i
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output logic cpu_addr_sel_o
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);
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);
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logic ly_sel;
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logic ly_sel;
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logic [ 7:0] ly_r;
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logic ly_r;
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logic ly_we;
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logic ly_we;
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assign ly_sel = (cpu_addr_i == 16'hFF44);
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assign ly_sel = (cpu_addr_i == 16'hFF44);
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assign ly_we = ly_sel & cpu_we_i;
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assign ly_we = ly_sel & cpu_we_i;
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@ -25,6 +22,6 @@ always_ff @(posedge clk or negedge nreset) begin
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ly_r <= 8'h90;
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ly_r <= 8'h90;
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end
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end
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assign cpu_addr_sel_o = ly_sel;
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assign cpu_rdata_o = {8{ly_sel}} & ly_r;
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endmodule : ppu
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endmodule : ppu
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21
rtl/ram.sv
21
rtl/ram.sv
@ -3,7 +3,9 @@ module ram #(
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parameter ADDR_W = 8
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parameter ADDR_W = 8
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)(
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)(
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input logic clk,
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input logic clk,
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input logic nreset,
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input logic cs_i,
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input logic [ADDR_W-1:0] address_i,
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input logic [ADDR_W-1:0] address_i,
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input logic we_i,
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input logic we_i,
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input logic [DATA_W-1:0] wdata_i,
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input logic [DATA_W-1:0] wdata_i,
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@ -16,13 +18,22 @@ logic [DATA_W-1:0] ram [RAM_SIZE-1:0];
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logic [DATA_W-1:0] rdata;
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logic [DATA_W-1:0] rdata;
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always_ff @(posedge clk)
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logic we;
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if (we_i)
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assign we = cs_i & we_i;
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always_ff @(posedge clk) begin
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if (we)
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ram[address_i] <= wdata_i;
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ram[address_i] <= wdata_i;
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end
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always_ff @(posedge clk)
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always_ff @(posedge clk or negedge nreset) begin
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rdata <= ram[address_i];
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if (!nreset)
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rdata <= '0;
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else
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rdata <= ram[address_i];
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end
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assign rdata_o = rdata;
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assign rdata_o = {8{cs_i}} & rdata;
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endmodule
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endmodule
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13
rtl/rom.sv
13
rtl/rom.sv
@ -4,6 +4,9 @@ module rom #(
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parameter integer unsigned DATA_W = 8
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parameter integer unsigned DATA_W = 8
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) (
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) (
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input logic clk,
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input logic clk,
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input logic nreset,
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input logic cs_i,
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input logic [ADDR_W-1:0] address_i,
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input logic [ADDR_W-1:0] address_i,
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output logic [DATA_W-1:0] rdata_o
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output logic [DATA_W-1:0] rdata_o
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);
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);
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@ -13,10 +16,14 @@ localparam ROM_SIZE = 2**ADDR_W;
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logic [DATA_W-1:0] rom [ROM_SIZE-1:0];
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logic [DATA_W-1:0] rom [ROM_SIZE-1:0];
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logic [DATA_W-1:0] rdata;
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logic [DATA_W-1:0] rdata;
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always_ff @(posedge clk)
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always_ff @(posedge clk or negedge nreset) begin
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rdata <= rom[address_i];
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if (!nreset)
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rdata <= '0;
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else
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rdata <= rom[address_i];
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end
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assign rdata_o = rdata;
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assign rdata_o = {8{cs_i}} & rdata;
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initial begin
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initial begin
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static integer fd = $fopen(FILE_NAME, "rb");
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static integer fd = $fopen(FILE_NAME, "rb");
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