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Starting work on a simple cartridge

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In order to get through bootstrap process
This commit is contained in:
Koray Yanik
2023-10-02 21:56:19 +01:00
parent 5f98c7346f
commit 7cec002e1a
4 changed files with 80 additions and 12 deletions
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28
sim/tb_top.sv
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@@ -3,6 +3,14 @@ module tb_top;
logic clk;
logic nreset;
wire gb_cart_clk;
wire gb_cart_nreset;
wire gb_cart_nrd;
wire gb_cart_nwr;
wire gb_cart_ncs;
wire [15:0] gb_cart_addr;
wire [ 7:0] gb_cart_data;
clkgen clkgen_inst (
.clk (clk),
.nreset(nreset)
@@ -10,7 +18,25 @@ clkgen clkgen_inst (
gb gb_inst (
.clk (clk),
.nreset(nreset)
.nreset(nreset),
.cart_clk_o (gb_cart_clk),
.cart_nreset_o(gb_cart_nreset),
.cart_nrd_o (gb_cart_nrd),
.cart_nwr_o (gb_cart_nwr),
.cart_ncs_o (gb_cart_ncs),
.cart_addr_o (gb_cart_addr),
.cart_data_io (gb_cart_data)
);
cart cart_inst (
.clk (gb_cart_clk),
.nreset (gb_cart_nreset),
.nrd_i (gb_cart_nrd),
.nwr_i (gb_cart_nwr),
.ncs_i (gb_cart_ncs),
.addr_i (gb_cart_addr),
.data_io (gb_cart_data)
);
logic instr_valid;