Starting work on a simple cartridge

In order to get through bootstrap process

build/tb_top.Makefile

@@ -1,5 +1,5 @@
 TB       = tb_top
-SOURCES  = gb.sv cpu.sv ppu.sv idec.sv ctrl.sv alu.sv alu16.sv regbank.sv rom.sv ram.sv tb_top.sv clkgen.sv
+SOURCES  = gb.sv cpu.sv ppu.sv idec.sv ctrl.sv alu.sv alu16.sv regbank.sv rom.sv ram.sv cart.sv tb_top.sv clkgen.sv
 INCLUDES = cpu_pkg.svh sva_common.svh
 PATH_SRC = ../rtl:../rtl/cpu:../sim
 

rtl/cart.sv

@@ -0,0 +1,30 @@
+module cart (
+  input  wire        clk,
+  input  wire        nreset,
+  input  wire        nrd_i,
+  input  wire        nwr_i,
+  input  wire        ncs_i,
+  input  wire [15:0] addr_i,
+  inout  wire [ 7:0] data_io
+);
+
+logic cs;
+logic [ 7:0] rom_rdata;
+
+assign cs = ~ncs_i;
+
+assign data_io = (cs & ~nrd_i) ? rom_rdata : 'Z;
+
+rom #(
+  .FILE_NAME("tetris.gb"),
+  .ADDR_W   (14),
+  .DATA_W   (8)
+) rom_inst (
+  .clk      (clk),
+  .nreset   (nreset),
+  .cs_i     (cs),
+  .address_i(addr_i[13:0]),
+  .rdata_o  (rom_rdata)
+);
+
+endmodule : cart

rtl/gb.sv

@@ -1,16 +1,16 @@
 // Top level gb module
 module gb (
-  input  logic clk,
+  input  wire clk,
-  input  logic nreset,
+  input  wire nreset,
 
   // Cartridge bus
-  output  logic        cart_clk_o,
+  output  wire        cart_clk_o,
-  output  logic        cart_nreset_o,
+  output  wire        cart_nreset_o,
-  output  logic        cart_nrd_o,
+  output  wire        cart_nrd_o,
-  output  logic        cart_nwr_o,
+  output  wire        cart_nwr_o,
-  output  logic        cart_ncs_o,
+  output  wire        cart_ncs_o,
-  output  logic [15:0] cart_addr_o,
+  output  wire [15:0] cart_addr_o,
-  input   logic [ 7:0] cart_data_i
+  inout   wire [ 7:0] cart_data_io
 
 );
 
@@ -31,6 +31,9 @@ logic [ 7:0] hiram_rdata;
 logic        vram_sel;
 logic [ 7:0] vram_rdata;
 
+logic        cart_sel;
+logic [ 7:0] cart_rdata;
+
 cpu cpu_inst (
   .clk    (clk),
   .nreset (nreset),
@@ -56,11 +59,13 @@ assign rom_enable_r = '1;
 assign rom_sel   = rom_enable_r & ~(|cpu_addr[15:8]);
 assign vram_sel  = (cpu_addr[15:13] == 3'b100);
 assign hiram_sel = (&cpu_addr[15:7]) & ~(&cpu_addr[6:0]);
+assign cart_sel  = (~cpu_addr[15]) & (~cpu_addr[14]) & (~rom_sel);
 
 assign cpu_rdata = rom_rdata     |
                    vram_rdata    |
                    hiram_rdata   |
-                   cpu_ppu_rdata;
+                   cpu_ppu_rdata |
+                   cart_rdata;
 
 rom #(
   .FILE_NAME("DMG_ROM.bin"),
@@ -100,6 +105,13 @@ ram #(
   .wdata_i   (cpu_wdata)
 );
 
+assign cart_rdata = cart_sel ? cart_data_io : '0;
 
+assign cart_clk_o    = clk;
+assign cart_nreset_o = nreset;
+assign cart_nrd_o    = 1'b0;
+assign cart_nwr_o    = 1'b1;
+assign cart_ncs_o    = ~cart_sel;
+assign cart_addr_o   = cpu_addr;
 
 endmodule : gb

sim/tb_top.sv

@@ -3,6 +3,14 @@ module tb_top;
 logic clk;
 logic nreset;
 
+wire        gb_cart_clk;
+wire        gb_cart_nreset;
+wire        gb_cart_nrd;
+wire        gb_cart_nwr;
+wire        gb_cart_ncs;
+wire [15:0] gb_cart_addr;
+wire [ 7:0] gb_cart_data;
+
 clkgen clkgen_inst (
   .clk   (clk),
   .nreset(nreset)
@@ -10,7 +18,25 @@ clkgen clkgen_inst (
 
 gb gb_inst (
   .clk   (clk),
-  .nreset(nreset)
+  .nreset(nreset),
+
+  .cart_clk_o   (gb_cart_clk),
+  .cart_nreset_o(gb_cart_nreset),
+  .cart_nrd_o   (gb_cart_nrd),
+  .cart_nwr_o   (gb_cart_nwr),
+  .cart_ncs_o   (gb_cart_ncs),
+  .cart_addr_o  (gb_cart_addr),
+  .cart_data_io (gb_cart_data)
+);
+
+cart cart_inst (
+  .clk     (gb_cart_clk),
+  .nreset  (gb_cart_nreset),
+  .nrd_i   (gb_cart_nrd),
+  .nwr_i   (gb_cart_nwr),
+  .ncs_i   (gb_cart_ncs),
+  .addr_i  (gb_cart_addr),
+  .data_io (gb_cart_data)
 );
 
 logic        instr_valid;