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Rename decoding signals to be more consistent 

r/n now always refers to 8bit registers, rr/nn to 16bit.
This commit is contained in:
Koray Yanik 2021-02-22 21:58:54 +00:00
parent dc32757dfc
commit bd8df33066
3 changed files with 43 additions and 36 deletions
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1
rtl/cpu/cpu.sv
View File

@ -128,6 +128,7 @@ module cpu (
assign address_o = (adr_src == ADR_SRC_HL) ? hl :
(adr_src == ADR_SRC_REG8) ? {8'hFF, reg8_rdata} :
(adr_src == ADR_SRC_REG16) ? reg16_rdata :
(adr_src == ADR_SRC_OPERAND8) ? {8'hFF, operand8} :
(adr_src == ADR_SRC_OPERAND16) ? operand16 :
pc;
assign wdata_o = (op_dest == OP_DEST_MEMORY) ? alu_operand :

1
rtl/cpu/cpu_pkg.svh
View File

@ -85,6 +85,7 @@ package cpu_pkg;
ADR_SRC_HL,
ADR_SRC_REG8, // extended with FF
ADR_SRC_REG16,
ADR_SRC_OPERAND8, // extended with FF
ADR_SRC_OPERAND16
} adr_src_t;

77
rtl/cpu/decode.sv
View File

@ -43,13 +43,14 @@ module decode (
logic is_cb;
logic is_ld_r_r;
logic is_ld_a_nn;
logic is_ld_r_nn;
logic is_ld_a_n;
logic is_ld_r_n;
logic is_ldh_c_a;
logic is_ld_rrrr_a;
logic is_ld_nnnn_a;
logic is_ld_rr_nnnn;
logic is_ld_sp_nnnn;
logic is_ldh_n_a;
logic is_ld_rr_a;
logic is_ld_nn_a;
logic is_ld_rr_nn;
logic is_ld_sp_nn;
logic is_ldd_hl_a;
logic is_alu_a_r;
logic is_bit_n_r;
@ -68,15 +69,16 @@ module decode (
assign is_cb = (instr0_i == 8'hCB);
assign is_ld_r_r = (dec_x == 2'h1) & ((dec_z != 3'h6) | (dec_y != 3'h6));
assign is_ld_a_nn = is_ld_r_nn & (reg8_dest == REG8_A);
assign is_ld_r_nn = (dec_x == 2'h0) & (dec_z == 3'h6);
assign is_ld_rr_nnnn = (dec_x == 2'h0) & (dec_z == 3'h1) & ~dec_q & (dec_p != 2'h3);
assign is_ld_sp_nnnn = (dec_x == 2'h0) & (dec_z == 3'h1) & ~dec_q & (dec_p == 2'h3);
assign is_ldd_hl_a = (dec_x == 2'h0) & (dec_z == 3'h2) & ~dec_q & (dec_p == 2'h3);
assign is_ld_rrrr_a = (dec_x == 2'h0) & (dec_z == 3'h2) & ~dec_q & (dec_p != 2'h3);
assign is_ld_nnnn_a = (dec_x == 2'h0) & (dec_z == 3'h2) & ~dec_q & (dec_p == 2'h2);
assign is_ldh_c_a = instr0_i == 8'hE2;
assign is_ld_r_r = (dec_x == 2'h1) & ((dec_z != 3'h6) | (dec_y != 3'h6));
assign is_ld_a_n = is_ld_r_n & (reg8_dest == REG8_A);
assign is_ld_r_n = (dec_x == 2'h0) & (dec_z == 3'h6);
assign is_ld_rr_nn = (dec_x == 2'h0) & (dec_z == 3'h1) & ~dec_q & (dec_p != 2'h3);
assign is_ld_sp_nn = (dec_x == 2'h0) & (dec_z == 3'h1) & ~dec_q & (dec_p == 2'h3);
assign is_ldd_hl_a = (dec_x == 2'h0) & (dec_z == 3'h2) & ~dec_q & (dec_p == 2'h3);
assign is_ld_rr_a = (dec_x == 2'h0) & (dec_z == 3'h2) & ~dec_q & (dec_p != 2'h3);
assign is_ld_nn_a = (dec_x == 2'h0) & (dec_z == 3'h2) & ~dec_q & (dec_p == 2'h2);
assign is_ldh_c_a = instr0_i == 8'hE2;
assign is_ldh_n_a = instr0_i == 8'hE0;
assign is_alu_a_r = (dec_x == 3'h2);
assign is_bit_n_r = (is_cb & instr1_i[7:6] == 2'h1);
@ -92,29 +94,30 @@ module decode (
reg8_t'(dec_z);
assign reg8_dest = reg8_t'(dec_y);
assign need_instr1_o = is_ld_sp_nnnn | is_ld_rr_nnnn | is_cb | is_jr_cc_n | is_ld_r_nn;
assign need_instr2_o = is_ld_sp_nnnn | is_ld_rr_nnnn;
assign need_instr1_o = is_ld_sp_nn | is_ld_rr_nn | is_cb | is_jr_cc_n | is_ld_r_n | is_ldh_n_a;
assign need_instr2_o = is_ld_sp_nn | is_ld_rr_nn;
assign undef_o = ~(is_ld_r_r | is_ld_sp_nnnn | is_ld_rr_nnnn | is_alu_a_r | is_ldd_hl_a | is_bit_n_r | is_jr_cc_n | is_ld_r_nn | is_ldh_c_a | is_inc_r | is_ld_rrrr_a);
assign undef_o = ~(is_ldh_n_a | is_ld_r_r | is_ld_sp_nn | is_ld_rr_nn | is_alu_a_r | is_ldd_hl_a | is_bit_n_r | is_jr_cc_n | is_ld_r_n | is_ldh_c_a | is_inc_r | is_ld_rr_a);
assign sp_we_o = is_ld_sp_nnnn & (state_i == ST4_EXEC);
assign sp_we_o = is_ld_sp_nn & (state_i == ST4_EXEC);
assign alu_op_valid_o = is_alu_a_r | is_bit_n_r | is_ld_a_nn | is_inc_r;
assign alu_op_valid_o = is_alu_a_r | is_bit_n_r | is_ld_a_n | is_inc_r;
assign alu_op_o = is_bit_n_r ? ALU_OP_BIT :
is_ld_a_nn ? ALU_OP_NOP :
is_ld_a_n ? ALU_OP_NOP :
is_inc_a ? ALU_OP_INC :
is_inc_r ? ALU_OP_INCR :
alu_op_t'({1'b0, dec_y});
assign reg_write_alu_o = is_inc_r;
assign op_dest_o = (is_ld_r_r & reg8_dest == REG8_PHL) ? OP_DEST_MEMORY :
(is_ld_r_nn & reg8_dest == REG8_PHL) ? OP_DEST_MEMORY :
(is_ld_r_n & reg8_dest == REG8_PHL) ? OP_DEST_MEMORY :
(is_ld_r_r & reg8_dest == REG8_A) ? OP_DEST_A :
is_ld_r_r ? OP_DEST_REG8 :
is_ld_a_nn ? OP_DEST_A :
is_ld_r_nn ? OP_DEST_REG8 :
is_ld_a_n ? OP_DEST_A :
is_ld_r_n ? OP_DEST_REG8 :
is_ldh_c_a ? OP_DEST_MEMORY :
is_ld_rr_nnnn ? OP_DEST_REG16 :
is_ldh_n_a ? OP_DEST_MEMORY :
is_ld_rr_nn ? OP_DEST_REG16 :
is_ldd_hl_a ? OP_DEST_REG16 :
is_inc_a ? OP_DEST_A :
is_inc_r ? OP_DEST_REG8 :
@ -125,9 +128,10 @@ module decode (
(is_alu_a_r & reg8_src != REG8_A) ? OP_SRC_REG8 :
(is_ld_r_r & reg8_src == REG8_PHL) ? OP_SRC_MEMORY :
is_inc_r ? OP_SRC_REG8 :
is_ld_r_nn ? OP_SRC_OPERAND8 :
is_ld_r_n ? OP_SRC_OPERAND8 :
is_ldh_c_a ? OP_SRC_A :
is_ld_rr_nnnn ? OP_SRC_OPERAND16 :
is_ldh_n_a ? OP_SRC_A :
is_ld_rr_nn ? OP_SRC_OPERAND16 :
is_ldd_hl_a ? OP_SRC_REG16 :
is_bit_n_r ? OP_SRC_REG8 :
op_src_t'('X);
@ -140,17 +144,18 @@ module decode (
assign pc_src_o = is_jr_cc_n ? PC_SRC_OPERAND8 :
PC_SRC_SEQ;
assign adr_src_o = (is_ld_r_r & reg8_dest == REG8_PHL) ? ADR_SRC_HL :
(is_ld_r_r & reg8_src == REG8_PHL) ? ADR_SRC_HL :
is_ldd_hl_a ? ADR_SRC_HL :
(is_ld_r_nn & reg8_dest == REG8_PHL) ? ADR_SRC_HL :
is_ldh_c_a ? ADR_SRC_REG8 :
is_ld_nnnn_a ? ADR_SRC_OPERAND16 :
is_ld_rrrr_a ? ADR_SRC_REG16:
ADR_SRC_PC;
assign adr_src_o = (is_ld_r_r & reg8_dest == REG8_PHL) ? ADR_SRC_HL :
(is_ld_r_r & reg8_src == REG8_PHL) ? ADR_SRC_HL :
is_ldd_hl_a ? ADR_SRC_HL :
(is_ld_r_n & reg8_dest == REG8_PHL) ? ADR_SRC_HL :
is_ldh_c_a ? ADR_SRC_REG8 :
is_ldh_n_a ? ADR_SRC_OPERAND8 :
is_ld_nn_a ? ADR_SRC_OPERAND16 :
is_ld_rr_a ? ADR_SRC_REG16:
ADR_SRC_PC;
assign cc_o = cc_t'(dec_y[1:0]);
assign memory_we_o = is_ldd_hl_a | is_ldh_c_a | is_ld_rrrr_a | (is_ld_r_nn & reg8_dest == REG8_PHL) | (is_ld_r_r & reg8_dest == REG8_PHL);
assign memory_we_o = is_ldd_hl_a | is_ldh_c_a | is_ldh_n_a | is_ld_rr_a | (is_ld_r_n & reg8_dest == REG8_PHL) | (is_ld_r_r & reg8_dest == REG8_PHL);
endmodule : decode