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Koray Yanik bd8df33066 Rename decoding signals to be more consistent 
r/n now always refers to 8bit registers, rr/nn to 16bit.
2021-02-22 21:58:54 +00:00
build
Initial register bank, support LD RR, $nnnn instructions
2021-02-17 22:40:24 +00:00
rtl
Rename decoding signals to be more consistent
2021-02-22 21:58:54 +00:00
sim
Implement LD ($FF00+C), A
2021-02-20 22:10:47 +00:00
synthflow @ 767277e341
Initial work on build system
2021-02-15 21:40:12 +00:00
.gitignore
Implement ld r, r
2021-02-22 21:43:22 +00:00
.gitmodules
Initial work on build system
2021-02-15 21:40:12 +00:00
README.md
Initial commit
2021-02-15 14:54:08 +01:00

README.md

svgb

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Readme 122 KiB
Languages
SystemVerilog 88%
C 11.5%
Makefile 0.5%