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build
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Initial register bank, support LD RR, $nnnn instructions
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2021-02-17 22:40:24 +00:00 |
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rtl
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Rename decoding signals to be more consistent
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2021-02-22 21:58:54 +00:00 |
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sim
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Implement LD ($FF00+C), A
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2021-02-20 22:10:47 +00:00 |
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synthflow@767277e341
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Initial work on build system
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2021-02-15 21:40:12 +00:00 |
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.gitignore
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Implement ld r, r
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2021-02-22 21:43:22 +00:00 |
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.gitmodules
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Initial work on build system
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2021-02-15 21:40:12 +00:00 |
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README.md
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Initial commit
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2021-02-15 14:54:08 +01:00 |
