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e713f8de87
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Implement RLA and POP RR
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2022-02-08 23:53:02 +00:00 |
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da29d148bf
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Update synthflow and adapt makefile
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2022-02-08 16:14:13 +00:00 |
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2937ff492b
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Initial register bank, support LD RR, $nnnn instructions
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2021-02-17 22:40:24 +00:00 |
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237a5f1489
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Implemented SP, $nnnn and XOR A instructions
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2021-02-16 23:05:46 +00:00 |
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aa92344d10
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Initial work on decoder
Decode the LD SP, $nnnn instruction as our first three-byte
instruction.
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2021-02-16 21:13:50 +00:00 |
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3191a19f7e
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Initial work on reading instructions from bootROM
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2021-02-15 22:55:09 +00:00 |
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e56afb8c9e
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Initial work on build system
Simple makefile to build testbench in vivado.
Testbench currently just has a clock and a reset.
Empty gb top module.
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2021-02-15 21:40:12 +00:00 |
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