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• 82584dab34 More WIP on PPU master Koray Yanik 2023-10-31 22:48:14 +0000
• 3c3dbd2175 Starting work on PPU -> display -> VGA Koray Yanik 2023-10-13 20:46:05 +0100
• bfcdec1d83 Add a simple watchdog timeout Koray Yanik 2023-10-03 22:31:39 +0100
• 9cc63a248e Fix some verilog issues Koray Yanik 2023-10-03 22:30:36 +0100
• 06746f71fb WIP PPU LX/LY registers Koray Yanik 2023-10-03 20:44:28 +0100
• 118f6b41b8 WIP on PPU io registers Koray Yanik 2023-10-02 22:47:32 +0100
• 7cec002e1a Starting work on a simple cartridge Koray Yanik 2023-10-02 21:56:19 +0100
• 5f98c7346f Add chip selects to rom/ram Koray Yanik 2023-10-02 21:23:39 +0100
• fda176d3b5 Complete rewrite from scratch, bootstrap WIP Koray Yanik 2023-10-01 23:00:56 +0100
• e713f8de87 Implement RLA and POP RR Koray Yanik 2022-02-08 23:53:02 +0000
• 4f892eb3f2 Implement RL r instruction Koray Yanik 2022-02-08 16:14:57 +0000
• da29d148bf Update synthflow and adapt makefile Koray Yanik 2022-02-08 16:14:13 +0000
• c8756dafa6 Implement push rr Koray Yanik 2021-02-23 22:38:10 +0000
• f6e68231fd Implement call nn Koray Yanik 2021-02-22 23:07:10 +0000
• 7e558104de Implement ld a, rr Koray Yanik 2021-02-22 22:20:47 +0000
• bd8df33066 Rename decoding signals to be more consistent Koray Yanik 2021-02-22 21:58:54 +0000
• dc32757dfc Implement ld r, r Koray Yanik 2021-02-22 21:42:40 +0000
• ded64a8954 Implement inc r Koray Yanik 2021-02-20 22:57:15 +0000
• 49ce1631b3 Implement LD ($FF00+C), A Koray Yanik 2021-02-20 22:10:47 +0000
• b1b2055db9 Fix another bug in 8bit register writing Koray Yanik 2021-02-20 20:52:02 +0000
• 67578ab87f Fix bug in registers when loading 8bit values Koray Yanik 2021-02-20 15:56:38 +0000
• 67361093ec Implement LD r, $nn Koray Yanik 2021-02-20 15:56:22 +0000
• 7327ecffb9 Implement JR CC, $nn Koray Yanik 2021-02-20 15:00:01 +0000
• 93912e2089 Implemented BIT $n, r Koray Yanik 2021-02-19 21:53:13 +0000
• 8c65e4a669 Fix some typo's Koray Yanik 2021-02-19 21:30:13 +0000
• 8f0b8d3a48 Implemented LDD (HL), A Koray Yanik 2021-02-18 23:22:26 +0000
• 3e92cf5eec Fix LD RR,$nnnn instruction not reading operand Koray Yanik 2021-02-18 09:27:17 +0000
• 2937ff492b Initial register bank, support LD RR, $nnnn instructions Koray Yanik 2021-02-17 22:40:24 +0000
• 237a5f1489 Implemented SP, $nnnn and XOR A instructions Koray Yanik 2021-02-16 23:05:46 +0000
• aa92344d10 Initial work on decoder Koray Yanik 2021-02-16 21:13:50 +0000
• 3191a19f7e Initial work on reading instructions from bootROM Koray Yanik 2021-02-15 22:55:09 +0000
• e56afb8c9e Initial work on build system Koray Yanik 2021-02-15 21:40:12 +0000
• 1a6259caa1 Initial commit fumyuun 2021-02-15 14:54:08 +0100