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bfcdec1d8305356c652de835de27be75b399f2de
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Koray Yanik bfcdec1d83 Add a simple watchdog timeout
2023-10-03 22:31:39 +01:00
build
WIP PPU LX/LY registers
2023-10-03 20:44:28 +01:00
rtl
Fix some verilog issues
2023-10-03 22:30:36 +01:00
sim
Add a simple watchdog timeout
2023-10-03 22:31:39 +01:00
synthflow @ 1486728ced
Complete rewrite from scratch, bootstrap WIP
2023-10-01 23:00:56 +01:00
.gitignore
Complete rewrite from scratch, bootstrap WIP
2023-10-01 23:00:56 +01:00
.gitmodules
Initial work on build system
2021-02-15 21:40:12 +00:00
README.md
Initial commit
2021-02-15 14:54:08 +01:00

README.md

svgb

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Description
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Readme 122 KiB
Languages
SystemVerilog 88%
C 11.5%
Makefile 0.5%