bfcdec1d83
Add a simple watchdog timeout
2023-10-03 22:31:39 +01:00
9cc63a248e
Fix some verilog issues
2023-10-03 22:30:36 +01:00
06746f71fb
WIP PPU LX/LY registers
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Removed second reg16 read port - no longer needed.
2023-10-03 20:44:28 +01:00
118f6b41b8
WIP on PPU io registers
2023-10-02 22:47:32 +01:00
7cec002e1a
Starting work on a simple cartridge
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In order to get through bootstrap process
2023-10-02 21:56:19 +01:00
5f98c7346f
Add chip selects to rom/ram
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Slightly easier to work with ppu and cart memory spaces this way
2023-10-02 21:23:39 +01:00
fda176d3b5
Complete rewrite from scratch, bootstrap WIP
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Rewrite to use several bus multiplexers, resulting into a less messy
microarchitecture (hopefully). Some more room for cleanup though...
Supports every instruction from the bootstrap rom, more or less.
LY hacked at 0x90 to progress through vsync instantly.
No cartridge is present yet, so we will always fail checksum test and lock up.
2023-10-01 23:00:56 +01:00
e713f8de87
Implement RLA and POP RR
2022-02-08 23:53:02 +00:00
4f892eb3f2
Implement RL r instruction
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Some groundwork on rotation operations
2022-02-08 16:14:57 +00:00
da29d148bf
Update synthflow and adapt makefile
2022-02-08 16:14:13 +00:00
c8756dafa6
Implement push rr
2021-02-23 22:38:10 +00:00
f6e68231fd
Implement call nn
2021-02-22 23:07:10 +00:00
7e558104de
Implement ld a, rr
2021-02-22 22:20:47 +00:00
bd8df33066
Rename decoding signals to be more consistent
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r/n now always refers to 8bit registers, rr/nn to 16bit.
2021-02-22 21:58:54 +00:00
dc32757dfc
Implement ld r, r
2021-02-22 21:43:22 +00:00
ded64a8954
Implement inc r
2021-02-20 22:57:15 +00:00
49ce1631b3
Implement LD ($FF00+C), A
2021-02-20 22:10:47 +00:00
b1b2055db9
Fix another bug in 8bit register writing
2021-02-20 20:52:02 +00:00
67578ab87f
Fix bug in registers when loading 8bit values
2021-02-20 15:56:38 +00:00
67361093ec
Implement LD r, $nn
2021-02-20 15:56:22 +00:00
7327ecffb9
Implement JR CC, $nn
2021-02-20 15:55:31 +00:00
93912e2089
Implemented BIT $n, r
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First of the CB prefixed opcodes.
2021-02-19 21:53:13 +00:00
8c65e4a669
Fix some typo's
2021-02-19 21:49:38 +00:00
8f0b8d3a48
Implemented LDD (HL), A
2021-02-18 23:22:26 +00:00
3e92cf5eec
Fix LD RR,$nnnn instruction not reading operand
2021-02-18 09:27:17 +00:00
2937ff492b
Initial register bank, support LD RR, $nnnn instructions
2021-02-17 22:40:24 +00:00
237a5f1489
Implemented SP, $nnnn and XOR A instructions
2021-02-16 23:05:46 +00:00
aa92344d10
Initial work on decoder
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Decode the LD SP, $nnnn instruction as our first three-byte
instruction.
2021-02-16 21:13:50 +00:00
3191a19f7e
Initial work on reading instructions from bootROM
2021-02-15 22:55:09 +00:00
e56afb8c9e
Initial work on build system
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Simple makefile to build testbench in vivado.
Testbench currently just has a clock and a reset.
Empty gb top module.
2021-02-15 21:40:12 +00:00
1a6259caa1
Initial commit
2021-02-15 14:54:08 +01:00
