Koray Yanik
e56afb8c9e
Simple makefile to build testbench in vivado. Testbench currently just has a clock and a reset. Empty gb top module.
22 lines
313 B
Systemverilog
22 lines
313 B
Systemverilog
module tb_top ();
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logic clk;
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logic nreset;
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gb gb_inst (
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.clk_i (clk),
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.nreset_i(nreset)
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);
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initial begin
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clk = 1'b0;
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nreset = 1'b1;
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#1 nreset = 1'b0;
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#24 nreset = 1'b1;
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end // initial
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always #5 clk = ~clk;
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endmodule : tb_top
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