svgb/sim/tbench/tb_top.sv

module tb_top ();

    logic clk;
    logic nreset;

    gb gb_inst (
        .clk_i   (clk),
        .nreset_i(nreset)
    );

    initial begin
        clk    = 1'b0;
        nreset = 1'b1;

        #1  nreset = 1'b0;
        #24 nreset = 1'b1;
    end // initial

    always #5 clk = ~clk;

endmodule : tb_top