-
4a2d2b4881
Restructured Amaranth code to be able to import sibling modules
master
Roflin
2022-01-22 19:28:29 +01:00
-
7780e14887
Fix SP1 connector mirror mistake
Roflin
2022-01-22 19:21:35 +01:00
-
386602a63c
Fixes clock cycle delay in propagation of ExiClockState
Roflin
2022-01-11 22:47:25 +01:00
-
43fb4beb6e
Makes a seperate component that handles the ExiClk
Roflin
2022-01-09 22:42:14 +01:00
-
f7106abe87
Made new top level design which uses the shiftregister and connects leds and buttons
Roflin
2022-01-09 17:07:56 +01:00
-
e0f186c304
Restructured the amaranth HDL files.
Roflin
2022-01-09 15:12:27 +01:00
-
fd323b44e1
Initial commit.
Roflin
2022-01-07 23:15:38 +01:00