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• 4a2d2b4881 Restructured Amaranth code to be able to import sibling modules master Dennis Brentjes 2022-01-22 19:28:29 +0100
• 7780e14887 Fix SP1 connector mirror mistake Dennis Brentjes 2022-01-22 19:21:35 +0100
• 386602a63c Fixes clock cycle delay in propagation of ExiClockState Dennis Brentjes 2022-01-11 22:47:25 +0100
• 43fb4beb6e Makes a seperate component that handles the ExiClk Dennis Brentjes 2022-01-09 22:42:14 +0100
• f7106abe87 Made new top level design which uses the shiftregister and connects leds and buttons Dennis Brentjes 2022-01-09 17:07:56 +0100
• e0f186c304 Restructured the amaranth HDL files. Dennis Brentjes 2022-01-09 15:12:27 +0100
• fd323b44e1 Initial commit. Dennis Brentjes 2022-01-07 23:15:38 +0100