Roflin
bad2b54574
Re-verified every open item against the current board: - All three critical findings (DO/DI swap, MDI termination incl. dampers + center-tap bypass, FTDI EEPROM resistors) now done in both schematic and PCB - marked resolved with review results - Marked verified-done: 12V cap ratings, 1% tolerances, .history ignore, fiducial check (absent - to add with debug pass) - Confirmed still open: ETH_RST pull-up, PR1 divider margin (R3 still 200k), RSET 12.4k vs 12.3k, TPS22810 CT, iceprog pin mapping, board PCF, debug LEDs/test points, mechanical fit, ordering options Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
207 lines
13 KiB
Markdown
207 lines
13 KiB
Markdown
# re-bba-rb board — open items from hardware review (2026-07-17)
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Full review of schematics + PCB against component datasheets (in
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`datasheets/`), the WIZnet W5100S reference schematic, and JLCPCB
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manufacturing limits. Status 2026-07-18: **all three critical findings fixed
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in schematic AND PCB** (ERC 0, DRC 0 errors / 0 unconnected / 0 parity);
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remaining work is the Functional/Broader/ordering lists below.
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## Critical — ALL RESOLVED (schematic + PCB, verified 2026-07-18)
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- [x] **EXI DO/DI swapped at J3 — FIXED 2026-07-17** (all copper unchanged).
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YAGCD SP1 naming is console-perspective: pin 6 `DO` = GC data **out** →
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adapter's MOSI *input*; pin 9 `DI` = GC data **in** ← adapter's MISO
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*output* (verified via SD Gecko: MC pin 5 DO → SD CMD input; SD2SP2:
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DO → OR gate → SD CMD). Fix applied as a pure rename/identity swap:
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- [x] SP1 pin table in `docs/gc_bba_fpga_design.md` corrected (was the
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root cause) + MISO-tristate note updated.
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- [x] Net names EXI_MOSI(_RAW) ↔ EXI_MISO(_RAW) swapped across
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`exi.kicad_sch`, `Fpga.kicad_sch`, root sheet, and the PCB — this
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also swaps the D2 (PUSB3AB6) channel assignments by name.
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- [x] R21 (22 Ω) ↔ R25 (33 Ω) identities swapped between the two
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positions so 33 Ω stays on the FPGA-driven MISO line and 22 Ω on
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the MOSI input.
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- [x] Verified: ERC 0, DRC 0 (incl. schematic parity 0), netlist:
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J3.6(DO)→R21(22Ω)→**FPGA pin 4 (IOB_8a) = EXI_MOSI in**;
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J3.9(DI)→R25(33Ω)→**FPGA pin 3 (IOB_9b) = EXI_MISO out**.
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- [ ] Use this final pin map when writing the board PCF (see Broader
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items): MOSI = pin 4, MISO = pin 3, CLK = 44 (G6), CS = 45,
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INT = 46.
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- [x] **W5100S MDI termination network — DONE (schematic + PCB)**: added
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R26/R27 (49.9 Ω 1%, LCSC C25120) from
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TXOP/TXON to a common node + C18 (100 nF) to GND, and R28/R29 + C19 for
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RXIP/RXIN, on the PHY-side nets per the WIZnet reference schematic.
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ERC 0; netlist verified. PCB rework REVIEWED 2026-07-18 — PASS:
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- [x] Termination placed at U11's MDI edge (R26–R29 ~1–3 mm from pins,
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C18/C19 2.8 mm from their resistor pairs); stubs short; DRC 0
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errors incl. ETH_DP impedance rules; pair skew TX 0.30 mm /
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RX 0.72 mm; pairs on F.Cu over solid In1 GND (one short B.Cu
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crossover via per N line at the jack — fine).
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- [x] D4/D5 flow-through verified pad-by-pad (PHY side faces U11,
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cable side faces J2); In1 plane correctly voided under the
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magjack's cable/isolation side, all layers clear there.
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- [x] 3.3 Ω series dampers (WIZnet note 6) — DONE 2026-07-18: R32–R35
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(YAGEO RC0402FR-073R3L, LCSC C137986) in line U11→transformer;
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chip-side nets stay PHY_*, D4/D5-side renamed MDI_* (patterns
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added to ETH_DP netclass in .kicad_pro). Inserted in-line on the
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PCB, each in its own line row; MDI_* stubs 1.45–1.48 mm, no new
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vias; pair skew after insertion TX 0.66 mm / RX 1.81 mm (fine).
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- [x] Center-tap bypass (WIZnet note 7) — DONE 2026-07-18: C20 100 nF
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(C1525) + C21 1 µF 0603 (C15849) on ETH_3V3, placed against
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J2's pin column — as close to pins 4/5 as the In1 plane void
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allows while keeping short GND vias.
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- [x] D4/D5 (USBLC6 on the PHY pairs) — RESOLVED 2026-07-17: **keep,
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exactly as drawn.** ST explicitly rates USBLC6 for Ethernet;
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PHY-side placement guards residual coupling through the
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transformer; 2.5–3.5 pF/line is fine at 100BASE-TX. Two
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deliberate details, do not "fix": (1) pin 5 (VBUS) floats ON
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PURPOSE — the lines carry ~3.3 V DC bias (center taps) and swing
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above it; a 3.3 V-tied rail would clip signal peaks. Floating,
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the rail self-biases to the line peak and the internal 6 V zener
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still clamps strikes. (2) The split nets (PHY_* vs ETH_*) force
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FLOW-THROUGH routing (pins 1→6, 3→4 are one internal node) —
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zero-stub clamping; do NOT merge the nets or tap the diode as a
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stub (stub inductance adds L·di/dt let-through). Layout: route
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the pair in-line through the package, near J2, short GND via on
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pin 2. If ever bypassing at bring-up: desolder + jumper 1–6/3–4.
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- [x] **FT2232H EEPROM interface — DONE (schematic + PCB)** per datasheet
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Table 3.4: U7.4 (DO) moved to new net EE_DO; R30 (2.2 kΩ, C25879)
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inserted EE_DO→EE_DATA; R31 (10 kΩ, C25744) pull-up EE_DO→3V3.
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EEDATA→DI stays direct. R30/R31 placed 4–5 mm from U7, routed, DRC
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parity 0. ERC 0, netlist verified, BOM fields populated.
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## Functional / robustness
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- [ ] **iceprog pin mismatch**: iceprog hardcodes CS=ADBUS4, CDONE=ADBUS6,
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CRESET=ADBUS7. Board uses FLASH_CS=ADBUS3, CDONE=ACBUS1, CRESET=ACBUS0.
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Rewire to the iCEbreaker convention, or maintain a patched iceprog.
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- [ ] **TPS2116 PR1 divider margin**: 200k/100k gives PR1 = 1.10 V vs
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VREF = 1.0 V ±8 % (max 1.08 V) — 20 mV worst-case margin against the
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3.3 V buck output. Change R3 to 150 k → switchover at 2.30–2.70 V.
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- [ ] **ETH_RST pull-up**: W5100S RSTn is a plain input (no internal pull) and
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floats while the FPGA configures. Add 10 k to **ETH_3V3** (not 3V3, so
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it sits low when the ETH rail is off).
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- [ ] **Gateware: gate all outputs on GC_ON** — when GC_ON=0 the W5100S is
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unpowered (U12) and the GC is off, but FPGA banks stay at 3.3 V. Hold
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the W5100S bus and EXI outputs Hi-Z/low to avoid back-powering.
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- [ ] **Gateware: UART crossover** — net names are FT-perspective
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(UART_TXD = FTDI output = FPGA **RX** on pin 18). Get this right in the
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board PCF.
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- [ ] **Gateware: EXI INT drive style** — prefer open-drain emulation (drive
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low / release) on J3.3 rather than push-pull high.
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## Broader items (beyond the wiring review — block fab on the first two)
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- [ ] **Write the re-bba-rb pin constraints** — `exi_bba/synth.py` still targets
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the iCEbreaker. This board: EXI on FPGA pins 3 (IOB_9b), 4 (IOB_8a),
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44 (EXI_CLK, G6), 45 (EXI_CS), 46 (EXI_INT); W5100S bus on the IOT bank
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(23–43); CLK12 on 20 (G3); GC_ON on 21; ETH_RST on 2; UART on 18/19.
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This is where the DO/DI swap and the UART crossover (UART_TXD = FTDI
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output = FPGA RX) get resolved. Pure software; do it before ordering to
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prove the pinout.
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- [ ] **Add debug provisions — the board currently has none.** RGB0–2 are
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unconnected, no LEDs, no button, no test points; the CLAUDE.md bring-up
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plan (StatusPanel heartbeat/activity LEDs + BTN re-init) has nothing to
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drive. Spare IOBs: 6, 9, 10, 11, 12, 13, 47, 48. Add ≥2 LEDs (heartbeat,
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EXI activity), a 4–6 pin debug header (logic-analyzer access — EXI
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CLK/CS/MOSI/MISO are what you probe when enumeration fails), and test
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points on 3V3 / 1V2 / ETH_3V3 / GC_ON. Cannot be retrofitted.
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- [ ] **Verify mechanical fit** — outline + finger geometry vs SP1ETH/ETH2SP1
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references (per CLAUDE.md), RJ45 and USB-C protrusion vs the GC serial
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port bay opening. An earlier commit says "need to remeasure PCB outline";
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sp1_test_plug validates pads only, not the envelope.
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- [x] **SP1 12 V rail viability — VERIFIED against existing projects
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(2026-07-17).** webhdx's IDE-EXI v2 for Serial Port 1 (which became the
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commercial M.2 Loader): "New switching power regulator supplies 3.3V@2A
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from 12V rail" (webhdx, gc-forever thread t=4843, 2021-08-28) — a
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shipping SP1 product powers an M.2 SATA SSD + RP2040 entirely from
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pin 5's 12 V through a buck, no external supply. That's the same
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architecture as this board at several times our load (~130 mA @ 12 V).
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webhdx moved from a linear regulator to a buck because the linear "was
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generating a lot of heat" — validating the TPS562201 choice. The
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official modem (DOL-014) was the original 12 V consumer; SP1ETH leaves
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12 V unused (runs from the 3.3 V pins). Remaining bench check only:
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- [ ] inrush into C65 (100 µF) + 2×10 µF buck input caps at GC power-on
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(the M.2 Loader precedent suggests this is a non-issue).
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- [ ] **Decide FT2232H EEPROM contents + flashing workflow** — blank 93LC46B
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enumerates with default VID/PID (works, generic); custom
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VID/PID/serial/product string needs FT_PROG provisioning. Tied to the
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iceprog-pin-mapping decision above (changes the schematic).
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- [ ] CC1/CC2 have no ESD protection (USBLC6 covers D+/D− only) — optional,
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most hobby designs skip; note spare-channel budget if respinning D2 area.
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- [x] `.history/` (embedded `.git`) — VERIFIED ignored via root
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`.gitignore:28`, nothing tracked.
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## Minor / BOM
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- [ ] RSET_BG: datasheet says 12.3 kΩ 1 % (ref schematic: 12 k + 300 Ω);
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board has 12.4 k (~0.8 % off). Match if convenient.
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- [x] Crystals Y1/Y2 — VERIFIED 2026-07-17: the BOM parts are both CL = 12 pF
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(Y1 YXC X322512MOB4SI / C70565, Y2 X322525MOB4SI / C9006, both JLC
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Basic, ±10 ppm) — correct for the 18 pF load caps and the W5100S
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Table 9 recommendation. No change needed.
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- [x] 12 V-rail parts ≥ 25 V — VERIFIED in BOM audit 2026-07-17: C3/C4 25 V,
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C6 50 V, C65 25 V (Lelon SMD electrolytic); D3 SMAJ12A correct.
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- [x] 1 % tolerance — VERIFIED in BOM audit 2026-07-17: R1/R2, R3/R4, R10,
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R16 are all 1 % UNI-ROYAL parts (and new R26–R35 are 1 %).
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- [ ] TPS22810 CT: floating = fastest ramp (~0.7 A inrush into ETH rail
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caps). Consider CT = 10 nF footprint (DNP-able).
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- [ ] Verify HR911105A internal LED pinout (assumed: 9/12 anodes via
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R14/R15 330 Ω to ETH_3V3, 10/11 cathodes to LNKn/ACTn) and the
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Bob-Smith common on pin 8 (tied straight to GND here; WIZnet ref
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separates chassis via 1 nF/2 kV — acceptable choice, confirm intent).
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- [ ] Confirm at bring-up (from CLAUDE.md): W5100S register addresses / MR
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bits were written from memory.
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## JLCPCB ordering notes (DRC clean — these are order-form options)
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- [ ] Stackup = JLC04121H-7628 (matches the 0.2104 mm prepreg / 0.6 mm core,
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~1.14 mm ≙ JLC nominal 1.2 mm — satisfies the SP1 slot's 1.2 mm spec).
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- [ ] Select **ENIG** (file has copper_finish "None") and **gold fingers +
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45° bevel** for the SP1 edge connector.
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- [ ] Hand-solder / non-economic-assembly parts: C65 (THT electrolytic),
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J2 magjack (THT), J1 USB-C, D2 (DFN2111-7, tiny). Plan assembly split.
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- [x] LCSC part numbers — COMPLETE 2026-07-17: all 112 orderable components
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have Footprint + Value + MPN + LCSC + Manufacturer (netlist-vs-BOM
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count check passes; the only netlist/BOM delta is J3, deliberately
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excluded from BOM since the SP1 edge connector is PCB gold fingers,
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not a part). 12 V-rail caps verified ≥25 V, divider/REF/RSET resistors
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verified 1 %. Note: D2 is the **ElecSuper** PUSB3AB6Z(ES) clone
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(C49383400, Extended), not Nexperia — same DFN-7 1.1×2.1 / 0.15 pF;
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pin-compatible, but treat as a bring-up suspect if EXI ESD behaviour
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looks odd. C65 is an SMD electrolytic (Lelon VZH101M1ETR-0607, 25 V) —
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assembly-friendly, not THT as first assumed.
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- [ ] Fiducials: VERIFIED ABSENT (0 on the board, 2026-07-18). JLCPCB can
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panel-add their own, but 3 board fiducials (1 mm copper dot, 2 mm mask
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opening, asymmetric corners) is the robust choice — add with the debug
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LEDs/test points pass.
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## Housekeeping (repo) — done 2026-07-17
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- [x] Restored `hardware/re-bba-rb/datasheets/` (deleted by `3547302`) from
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the LFS store; added TPS22810 (power/) and PUSB3AB6 (exi/) datasheets
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that were missing from the original set.
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- [x] Deleted stale lowercase `power.kicad_sch` (the pre-rework draft from the
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first power-sheet commit; live sheet is `Power.kicad_sch`). It "kept
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coming back" because both paths were git-tracked: on a case-insensitive
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(Windows) checkout they are one file on disk, so deleting one path also
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deletes the other, and restoring the live sheet re-materialises both —
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the next commit resurrects the stale path. Removing the lowercase path
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from the git index (done from the case-sensitive devcontainer) is the
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permanent fix. **Never add two files differing only in case.**
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- [x] Deleted `re-bba-rb.kicad_pcb.old.kicad_pcb` / `.old.kicad_pro` leftovers
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(recoverable from git history if ever needed).
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## Verified correct — do not re-flag
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TPS562201 (EN at 12 V legal, abs max 19 V; 0.768 V ref × 33k/10k = 3.30 V;
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L/C per Table 7-2) · TPS2116 mode/ST logic (GC priority, USB fallback,
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GC_ON polarity) · AP2112K ×2 · TPS22810 EN (never floats, R5 pull-up) ·
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**FT2232H VPHY/VPLL on 3.3 V is correct per datasheet** (the VCORE→3V3
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relabel at HEAD was a fix) · W5100S parallel-mode straps (MOD=0100, SCLK→GND,
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pin32=A0/pin33=A1, INTn push-pull, internal pull-ups on CSn/RDn/WRn/DAT) ·
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W5100S 1V2 loop + mandatory 1 MΩ crystal feedback · PUSB3AB6 pinout/footprint ·
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USB-C CC/ESD wiring · iCE40 power/config/flash, CLK12 on G3, EXI_CLK on G6 ·
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magjack transformer spec (1:1, 350 µH) · PCB vs JLCPCB capability floor
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(rules in `re-bba-rb.kicad_dru`, 0 DRC errors).
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