svgb/rtl/cpu/regbank.sv

`include "cpu_pkg.svh"

import cpu_pkg::*;

module regbank (
    input  logic clk,
    input  logic nreset,

    input  reg8_t reg8_wselect_i,
    input  logic  reg8_we_i,
    input  logic [ 7:0] reg8_wdata_i,

    input  reg16_t reg16_wselect_i,
    input  logic   reg16_we_i,
    input  logic [15:0] reg16_wdata_i,

    input  reg8_t reg8_rselect_i,
    input  reg16_t reg16_rselect_i,
    input  reg16_t reg16_rselect2_i,
    output logic [ 7:0] reg8_rdata_o,
    output logic [15:0] reg16_rdata_o,
    output logic [15:0] reg16_rdata2_o,

    output logic [15:0] hl_o
);

    logic [15:0] reg_r   [0:2];
    logic [15:0] reg_next;
    logic [ 1:0] reg_we  [0:2];

    generate for (genvar i = 0; i <= 2; i++) begin : gen_regs
        always_ff @(posedge clk or negedge nreset) begin
            if (!nreset) begin
                reg_r[i][7:0] <= '0;
            end else if (reg_we[i][0]) begin
                reg_r[i][7:0] <= reg_next[7:0];
            end
        end
        always_ff @(posedge clk or negedge nreset) begin
            if (!nreset) begin
                reg_r[i][15:8] <= '0;
            end else if (reg_we[i][1]) begin
                reg_r[i][15:8] <= reg_next[15:8];
            end
        end

        assign reg_we[i][0] = (reg16_we_i & (reg16_wselect_i == i[1:0])) |
                              (reg8_we_i  & (reg8_wselect_i  == {i[1:0], 1'b1}));
        assign reg_we[i][1] = (reg16_we_i & (reg16_wselect_i == i[1:0])) |
                              (reg8_we_i  & (reg8_wselect_i  == {i[1:0], 1'b0}));
    end endgenerate

    assign reg_next = ({16{reg8_we_i}}  & {reg8_wdata_i, reg8_wdata_i}) |
                      ({16{reg16_we_i}} & reg16_wdata_i);

    assign reg8_rdata_o  = reg8_rselect_i[0] ? reg_r[reg8_rselect_i[2:1]][ 7:0] :
                                               reg_r[reg8_rselect_i[2:1]][15:8];
    assign reg16_rdata_o  = reg_r[reg16_rselect_i];
    assign reg16_rdata2_o = reg_r[reg16_rselect2_i];

    assign hl_o = reg_r[REG16_HL];

`include "sva_common.svh"
`SVA_DEF_CLK(clk)
`SVA_DEF_NRESET(nreset)

`SVA_ASSERT_PROP_FATAL(regbank_write_reg_a,
  reg8_we_i |-> (reg8_wselect_i != REG8_A),
  "Register bank received write to register A"
)

`SVA_ASSERT_PROP_FATAL(regbank_write_reg_phl,
  reg8_we_i |-> (reg8_wselect_i != REG8_PHL),
  "Register bank received write to register (HL)"
)

`SVA_ASSERT_PROP_FATAL(regbank_write_reg_sp_af,
  reg16_we_i |-> (reg16_wselect_i != REG16_SP_AF),
  "Register bank received write to register SP/AF"
)

endmodule : regbank