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Fix another bug in 8bit register writing

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This commit is contained in:
Koray Yanik 2021-02-20 20:52:02 +00:00
parent 67578ab87f
commit b1b2055db9
1 changed files with 4 additions and 4 deletions
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8
rtl/cpu/registers.sv
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@ -44,10 +44,10 @@ module registers (
end
end
assign reg_we[i][0] = (reg16_we_i & (reg16_wselect_i == i)) |
(reg8_we_i & ({reg8_wselect_i, 1'b0} == i));
assign reg_we[i][1] = (reg16_we_i & (reg16_wselect_i == i)) |
(reg8_we_i & ({reg8_wselect_i, 1'b1} == i));
assign reg_we[i][0] = (reg16_we_i & (reg16_wselect_i == i[1:0])) |
(reg8_we_i & (reg8_wselect_i == {i[1:0], 1'b0}));
assign reg_we[i][1] = (reg16_we_i & (reg16_wselect_i == i[1:0])) |
(reg8_we_i & (reg8_wselect_i == {i[1:0], 1'b1}));
end endgenerate
assign reg_next = ({16{reg8_we_i}} & {reg8_wdata_i, reg8_wdata_i}) |