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Fix bug in registers when loading 8bit values

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This commit is contained in:
Koray Yanik 2021-02-20 15:56:38 +00:00
parent 67361093ec
commit 67578ab87f
1 changed files with 10 additions and 3 deletions
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13
rtl/cpu/registers.sv
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@ -31,9 +31,16 @@ module registers (
generate for (genvar i = 0; i <= 2; i++) begin : gen_regs
always_ff @(posedge clk_i or negedge nreset_i) begin
if (~nreset_i) begin
reg_r[i] <= '0;
end else if (|reg_we[i]) begin
reg_r[i]<= reg_next;
reg_r[i][7:0] <= '0;
end else if (reg_we[i][0]) begin
reg_r[i][7:0] <= reg_next[7:0];
end
end
always_ff @(posedge clk_i or negedge nreset_i) begin
if (~nreset_i) begin
reg_r[i][15:8] <= '0;
end else if (reg_we[i][1]) begin
reg_r[i][15:8] <= reg_next[15:8];
end
end